Good day,
We have a system using multiple ADS42JB69 devices and achieve multichip synchronization using JESD204B subclass 1. The input clocks and SYSREF signals are all aligned and the setup and hold time requirements of SYSREF relative to the input clocks are met. As I understand the LMFC periods should now all be in phase.
To start the CGS and ILA sequence the SYNC~ signal should be asserted and deasserted, respectively. We can easily achieve this across all devices within the aligned LMFC periods. In Figure 74 and 75 of the ADS42JB69 datasheet, setup and hold time requirements of the SYNC~ signal relative to the input clocks are given.
Is it necessary to meet these setup and hold time requirements if the SYNC~ signal can be applied to all devices within the aligned LMFC periods?
Kind regards,
Francois Tolmie
