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ADS5400 -Clock Timing Questions

Jeffery Day
Expert 3605 points

Other Parts Discussed in Thread: ADS5400, CDCE72010

I have a number of questions about the ADS5400 adc clock timing.  I think I asked them a while ago (many months), but I don't believe I ever got a thorough response, as the parts were still new and being characterized (I believe).  If you could help me out with these I'd be very grateful :

1)  The output sample clock prop delay is listed as between 700 and 1700 ps.  Does it vary that much from part to part, or does it really vary over temperature?  We will have a number of these on 1 board hooked to a few fpgas.  I'd like to know how much their sample clocks will vary from each other for alignment purposes.
 
2)  In div4 sample aligned mode,  will clockoutap vary that much between clockoutbp?  In dual bus mode aligned, can we just use clockoutap to register both buses in?
 
3) On reset, the potential is there for clockoutap to miss a pulse, correct?  Again we have the I/O going to an FPGA, and I'm pondering putting the clocks into an MMCM to help with clock delay and skew, as well as to generate divided clocks from the adc sample clock. 
 
4) Is there any indication, upon asserting reset, that we may have violated the setup and/or hold for the reset pulse?
 
5) It seems the reset does not influence the bist sequence at all, e.g. it doesn't reset the sequence, etc.  Correct?
 
6)  It seems reset just aligns the clock and provides a Sync notification, correct?
Thanks,
Jeff
  • 0
    TI__Mastermind 29220 points

    Jeff,

    1) The min to max prop delay of 700 to1700ps is across process, voltage and temperature.  so if you put two devices on one circuit board next to each other (such that their termperatures and voltages are nearly the same) then you would see much less min to max variation.  We have not broken out the characterization data for data sheet purposes into the three separate components, but we may consider doing that in certain cases in the future.

    2) In our TSW1200, we use dual bus mode with clock div4 aligned, and i use one clock (clock A) to register both buses and ignore the other clock .   The setup and hold times for data around the clock will be valid.  The clock prop delay parameter from question 1 is not an issue here, as clock and data will largely move together.  The prop delay parameter becomes an issue if you have multiple devices and want to use the clock from one device relative to another.  Or if you want to not use the output clock at all and want to use a delayed version of the sample clock to register the data.

    3) I'm not sure i undertand the question.  If you meet the setup and hold time for reset around the clock input, then things are deterministic.  I don't know what might be meant by missing a pulse in this context.

    4) i think if you missed setup or hold time such that a device did not 'see' the reset pulse on the clock cycle that you expected it to see it. then you would get an indication of that if you were to be watching the SYNC output.  So if you have two data converters and apply reset to both of them on the same clock cycle, then you would see the SYNC pulse from both of them at the same time.  Other than that, i don't think there would be a readily observable indication.

    5 and 6) Correct, reset just resets the clock division path and does not affect the data path.

    Regards,

    Richard P.

  • 0
    TI__Expert 3605 points

    Richard,

     

    One good question/answer seems to lead to anotherJ. Please see customer comments/questions in green.

     

    1) The min to max prop delay of 700 to1700ps is across process, voltage and temperature.  so if you put two devices on one circuit board next to each other (such that their temperatures and voltages are nearly the same) then you would see much less min to max variation.  We have not broken out the characterization data for data sheet purposes into the three separate components, but we may consider doing that in certain cases in the future.

    It would be a nice to know for multiple adc/fpga systems.  Out of curiosity, what is much less?


    2) In our TSW1200, we use dual bus mode with clock div4 aligned, and I use one clock (clock A) to register both buses and ignore the other clock .   The setup and hold times for data around the clock will be valid.  The clock prop delay parameter from question 1 is not an issue here, as clock and data will largely move together.  The prop delay parameter becomes an issue if you have multiple devices and want to use the clock from one device relative to another.  Or if you want to not use the output clock at all and want to use a delayed version of the sample clock to register the data.

    Good.  I'm tempted to use a delayed version, and to put the adc in BIST mode, alternate 1's, 0's, use the IODELAYS on the fpga (72 ps resolution per tap) and bit align the adc to meet setup and hold that way.

    3) I'm not sure I understand the question.  If you meet the setup and hold time for reset around the clock input, then things are deterministic.  I don't know what might be meant by missing a pulse in this context.

    The data sheet on p10 suggests that the clkoutap or clkoutbp realigns, and therefore misses a pulse off of reset.  If we were to route this clock into the pll on an fpga, that may or may not be an issue, such that we need to reset the pll to relock.


    4) I think if you missed setup or hold time such that a device did not 'see' the reset pulse on the clock cycle that you expected it to see it. then you would get an indication of that if you were to be watching the SYNC output.  So if you have two data converters and apply reset to both of them on the same clock cycle, then you would see the SYNC pulse from both of them at the same time.  Other than that, I don't think there would be a readily observable indication.

    Okay.

    5 and 6) Correct, reset just resets the clock division path and does not affect the data path.

    Is there any suggested way to sync up the BIST sources between different ADCs?

     

    Regards,

    Jeff

     

    From: Richard Prentice [mailto:noreply@e2e.ti.com]
    Sent: Thursday, September 30, 2010 2:47 PM
    To: int_highspeed_dataconv_forum@e2e.ti.com
    Subject: Re: [INT - High Speed Data Converters Forum] ADS5400 -Clock Timing Questions

     

    Jeff,

    1) The min to max prop delay of 700 to1700ps is across process, voltage and temperature.  so if you put two devices on one circuit board next to each other (such that their termperatures and voltages are nearly the same) then you would see much less min to max variation.  We have not broken out the characterization data for data sheet purposes into the three separate components, but we may consider doing that in certain cases in the future.

    2) In our TSW1200, we use dual bus mode with clock div4 aligned, and i use one clock (clock A) to register both buses and ignore the other clock .   The setup and hold times for data around the clock will be valid.  The clock prop delay parameter from question 1 is not an issue here, as clock and data will largely move together.  The prop delay parameter becomes an issue if you have multiple devices and want to use the clock from one device relative to another.  Or if you want to not use the output clock at all and want to use a delayed version of the sample clock to register the data.

    3) I'm not sure i undertand the question.  If you meet the setup and hold time for reset around the clock input, then things are deterministic.  I don't know what might be meant by missing a pulse in this context.

    4) i think if you missed setup or hold time such that a device did not 'see' the reset pulse on the clock cycle that you expected it to see it. then you would get an indication of that if you were to be watching the SYNC output.  So if you have two data converters and apply reset to both of them on the same clock cycle, then you would see the SYNC pulse from both of them at the same time.  Other than that, i don't think there would be a readily observable indication.

    5 and 6) Correct, reset just resets the clock division path and does not affect the data path.

    Regards,

    Richard P.


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  • 0 in reply to Jeffery Day
    TI__Mastermind 29220 points

    Hi,

    1) regarding the portion of the min to max skew over process, voltage and temperature - that is difficult to say without the characterization data to back up any thing i might say.  If this were one of our CMOS devices, a rough rule of thumb from what i have seen from a number of designs is that the variables of process, voltage and temp are each responsible for about 1/3 of the total.  But on a bipolar device such as this one, i am told that voltage plays a smaller role and temp a larger role.    I can't narrow it down better than that at this time.  Our characterization engineer brought up a point that maybe could be relevant to this discussion - the ADS5400 has a die temp reading that might be used to help dial in skew settings in the FPGA - but again it would probably need some characterization data over temp to make this option viable.

    3) Oh, i see.  By missing pulses, you mean the output clock.  Since we were talking about reset, I was thinking of the SYNC pulse output, and that should not be missed.  The figure on page 10 (also pages 9, 11 and 12) is trying to say that when the reset is seen by the device, the output clock may be stretched.  So yes, a clock pulse may be moved or in certain circumstances like in figure4 skipped entirely.  This might cause issues for a PLL based clock manager that might be locked to the output clock.  But these disruptions to the output clock will occur only if the reset pulse comes in at a time that requires the clock edges of the output clock to move, such as the first reset after a power up.  After that - if resets come in asynchronously and all ADCs see the reset pulse at the same cycle then they will all stretch the clock if necessary the same amount.  If there are periodic reset pulses on regular intervals such as clk/2 or clk/4 then the 'reset' pulse will 'reset' the clock position to the location the clock edge already is at, and there will be no disturbance to the clocking but there would be periodic SYNC outputs.   If you can generate a reset pulse that is one pulse for every four clock pulses, then the resulting SYNC pulses may be enough to tag the samples from each data converter and allow the device to device skew to be factored back out again.  Some clock buffer chips may have programmable outputs to output such divided down outputs, but it may be tough at 1GHz.  We can ask our Communications Clocking group if a device such as CDCE72010 or similar could do something like this.

    5)  I don't know of a way to reset and line up the test patterns between multiple devices.  Again, the SYNC pulse might be a better choice if we can generate an appropriate repeating reset pulse.

    Regards,

    Richard P.