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ADS1256: ADS1256

Part Number: ADS1256


I am writing code for the ADS1256 A/D converter. I am a little confused about writes to registers as depicted in Tables 24 and 23 of the data sheet. In particular I am writing code to initialize the status registers (table 23). My issue is with ADCON. Following the instructions of table 24, I bring CS low, write WREG (0101 rrrr) where rrrr is the register identifier to be written to (table 23). ADCON is identified as address 02h in table 23. So I write 0x52 to the command register followed by 0x00 for the data byte.

When I do this, my readings are all 5.0V. This is perplexing because the 0x00 is supposed to be the default value. I added a RREG line and read back the ADCON register, it reads 0x00 as it should.

If I comment out the two lines of code that write to ADCON, the readings are fine. It looks like the PGA bits are being written to.

I am sending a WREG write to the command register Ored with the address of the register to be addressed followed by a byte of configuration data. I then send another WREG write to the command register Ored with the address of the next register to be addressed and so on until all desired configuration registers have been written to. The text above Table 24 says “Additional command and data bytes may be shifted in without delay after the first command byte.” Does this apply to the writing of configuration data to the Table 23 configuration registers? Can they somehow be written without additional WREG commands? If so, perhaps my repeated WREG/DATA writes are somehow being concatenated and who knows what I am writing to who?

Should I raise CS between WREG commands? Help please..

  • Ignore, I figured it out. Wasn't writing second byte after WREG commands.
  • Hi Aubrey,

    No problem - I'm glad you were able to resolve your issue!

    NOTE: Toggling /CS between commands is optional. One benefit to doing so is that toggling /CS resets the SPI interface and can help correct any SPI communication errors that might arise in the case that a glitch occurs on SCLK, such that the ADC is 1 SCLK ahead of the MCU...However, if you're doing a read or write to multiple registers (i.e. the second command byte is non-zero), then /CS must stay low until you've completed sending the entire command (and only then may you toggle the /CS pin). I believe setting /CS high early will terminate the command and cause the ADC to ignore it.

    Let us know if you have any additional questions!

    Best regards,
    Chris