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ADC32RF42: ADC32RF42 operation at 250 MSPS with Bypass DDC

Vikas Kumar40
Intellectual 660 points
Part Number: ADC32RF42
Other Parts Discussed in Thread: ADS54J40, ADS54RF63, ADS5474

As per the datasheet , the device minimum sampling rate is 750 MSPS. But for my operation, I need dual channel 14 bit ADC for 1.1 GHz sampling at 250 MSPS. The device can be used or any limitation is there architecture side.

  • 0
    TI__Intellectual 785 points

    Hi,

    Minimum supported sampling clock frequency for this part is 750-MSPS. If your limitation is arising from serial output data rate, you may use decimation (DDC) feature of device to reduce it. However, if your sampling clock frequency is limited to 250-MSPS only, you may consider other parts such as ADS54J40 (minimum sampling rate 250-MSPS). At 1.1GHz, what's expected signal amplitude at ADC's analog inputs? What's the application?

    Regards,

    Sourabh

  • 0 in reply to Sourabh Gupta
    Intellectual 660 points
    Hi Sourabh

    I have used ADS54RF63 for the current application. Now I want to change the design for dual channel 14 bit. Without changing much in software side, I wanted to migrate to this design .Because of which, I put the sampling frequency limitation. At 1.1 GHz, the expected signal level after conditioning is expected around 7 dBm.
  • 0 in reply to Vikas Kumar40
    TI__Intellectual 785 points
    Hi,
    ADS54J40 uses JESD output interface whereas ADS54RF63 uses LVDS interface. When you migrate from LVDS to JESD you may need a receiver (ASIC or FPGA) which can latch and decode the JESD data of ADC. So you may have to redesign the receiver scheme.
    ADS54J40 can support -12dBFS input level at 1.1GHz which is nearly equal to 500mVpp. This part offers very good SFDR with lower power consumption. If power and SFDR are not a concern, and you want to stick to LVDS interface, you might evaluate ADS5474.
    Regards,
    Sourabh
  • 0 in reply to Sourabh Gupta
    Intellectual 660 points
    Receiver scheme side, any how I need to migrate for the dual channel approach.If I go with -12 dBFS, then I will be losing 9 dB dynamic range, correct ? Power is concern, as the IC need to be airborne qualified.ADS5474 is single channel.
  • 0 in reply to Vikas Kumar40
    TI__Intellectual 785 points
    Hi,
    Assuming you would terminate ADC with 50ohms (differential value), 10dBm power means 2Vpp which is full-scale voltage of ADC. Then, -12dBFS will correspond to -2dBm which is 9dB down from 7dBm. So yes, you would need to backoff the signal power by 9dB if you want to use ADS54J40. You may use digital gain feature of ADC to gain up signal later. You can contact me at sourabh.gupta@ti.com for further guidance.
    Regards,
    Sourabh