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PGA411-Q1: PGA411-Q1 LBIST Flag

Helmut Theuerkauf
Prodigy 30 points
Part Number: PGA411-Q1

On a custom design I implemented 6 PGA411-Q1 chips. I am trying to get this run with a resolver RE-15 that requires 7VRMS. Nevertheless the Exciter refuses to run in normal mode.

It just starts when FaultRes is pulled low, but the with a standard configuration. The steps I followed to see what is going on is as follows:

-Sett FaultRes to Low

- Enter DIAG mode

- Set FaultRes to High

-Program OVUV6 and CONTROL1 to ignore all errors

- Program Phase Reg to 7VRMS

-Enter Normal mode

After that I read out configuration and status registers and here is what I got:

ConfigurationVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVV

OVUV1:        8b40
EXTILIMITH_HI 1_2 : 5
EXTILIMITH_LO 1_2 : 5
EXTOUT_GL         : 8
OSHORT HI         : 0
OSHORT LO         : 0
-----------------------

OVUV2:        ed
DVMSENH:      5
DVMSENL:      5
TRDHL:        3
XEXT AMP:     0
-----------------------

OVUV3:        fcff
EXTOVT:       7
EXTUVT:       7
OOPENTHH:     7
OOPENTHL:     7
OVIZH:        3
OVIZL:        0
-----------------------

OVUV4:         7e2
AUTOPHASE CFG: 0
FSHORT CFG:    0
TEXTMON:       7
TSHORT:        7
VEXT CFG:      0
nBoostFF:      1
-----------------------

OVUV5:        1c00
TOPEN:        7
-----------------------

OVUV6:        3cf
BOOST_VEXT_MSK: 1
IZTHL:          7
LPETHH:         3
LPETHL:         3
-----------------------

TLOOP CFG:    514
DKI:    4
DKP:    4
MKP:    2
OHYS:   1
SENCLK: 0
-----------------------

AFE CFG:      5
GAINCOS:      1
GAINSIN:      1
-----------------------

PHASE CFG:    1800
EXTOUT:     0
EXTMODE:    2
EXTUVF CFG: 0
APEN:       1
PDEN:       0
PHASEDEMOD: 0
-----------------------

CONF1:        2
MODEVEXT:     2
NPLE:         0
SELFEXT:     0
-----------------------

CTRL1:        2ffe
CTRL1:        2ffe
-----------------------

CTRL2:        0
-----------------------

CTRL3:        0
-----------------------

CRCCALC CRC: ff
DEVCRC CRC: 0
CLCRC CRC: ce

Status VVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVv

Status1 Register:    0
SPI Status: 0
-----------------------
Status2 Register:    0
SORD:    0
SPRD:    0
-----------------------
-----------------------
Status3 Register:    0
-----------------------
Status4 Register:    141
OUTZ Monitor
OUTA Monitor
FAULT Pin Monitor
Logical BIST Fault
-----------------------

Status5 Register:    0
ORDANGLE:    0
ORDCLK:      0
PRD:         0
-----------------------
Status6 Register:    0
ORDVELO:     0
PRD:         0
-----------------------
Status7 Register:    4b
OptID1:    1
RevID:     3
DevState:  1
OfsCalFlt: 0
-----------------------

As you can see it claims there is a logical BIST error.

So my question is, what may cause this error?

In the trouble shooting guide they say to contact this e2e forum..which I do now..

Thanks

  • 0
    TI__Mastermind 23810 points
    Helmut,

    Thank you for contacting us. Seeing LBIST is unusual. You mentioned that you are using six PGA411 ICs in your design. Are they all on the same board? Are all of them exhibiting this issue, or have you seen this only on one IC?

    The LBIST fault will stay until a successful BIST is run. Have you tried running the LBIST manually by using the LBIST_EN bit? Make sure to wait long enough for the LBIST to complete before transitioning from diagnostic to normal mode.

    It is possible that your initialization routine is causing an issue. How long do you wait after powering the device before going back to diagnostics mode?

    Thanks,

    -Clancy
  • 0 in reply to Clancy Soehren
    Prodigy 30 points

    Clancy,

    thank you for the reply.

    Yes, all six PGAs are on one board. To handle them with the available pins on the micro controller, the FAULT an FAULTRES pins are routet through multiplexer / demultiplexer. Additionally the parallel data ORD0 to ORD12, PRD and ORD_CLK are all tied together as a bus. With VA0 and VA1 on the same Level (HI, or LO), the parallel signals should be HI-Z, so that should not cause any issues, I think ?!

    From cancelling reset I waited 10ms, because time for BIST was in the datasheet described to be 5.2 ms.

    Before applying the configuration and entering DIAG Mode the ABIST_EN and LBIST_EN in CONTROL_REG2 are checked to be 0.
    Note:
    During polling the BIST_EN bits the FAULT_RES Pin is pulled low to make sure the device will answer, even if any Fault exists. The FAULT_RES pin is then released after the bits both found to be 0 and succesful switch to DIAG Mode has been performed.

    Up to now I didn't try to run LBIST manually, but of course, I could try this, to see if it is somehow related with all the chips performing the built in tests at the same time..

    Thanks and Best Regards,

    Helmut

  • 0 in reply to Helmut Theuerkauf
    TI__Mastermind 23810 points
    Helmut,

    Were you able to debug your issue? Did you try running the LBIST manually?

    Thanks,

    -Clancy
  • 0 in reply to Clancy Soehren
    Prodigy 30 points
    Hi,
    no, I tried a new revision with layout more like stated in the datasheet. Result was even worse. With FaultRes Pin set to GND the devices heated up immediately, so in lack of time I threw the design away and completely removed the PGAs. Replacement will most likely be from Analog Devices..
  • 0 in reply to Helmut Theuerkauf
    TI__Mastermind 23810 points

    Thanks for the update. If the ICs are heating up, then it really sounds like a problem with the board. I would be happy to review your schematic if you send it to me through private message.

    However you proceed, good luck!