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ADS54J66: 40x JESD Mode Question

Troy Robinson
Prodigy 80 points

Part Number: ADS54J66
Other Parts Discussed in Thread: ADS54J64

I am asking for confirmation of the JESD Mode and JESD PLL mode of 40x that is given for the LMF = 484 (Mode 0) in Table 13 of the ADS54J66 datasheet.

This is what I can interpret from the ADS54J66 datasheet.

All clocks internally are referenced from the CLIN that directly drives ADC as a sample clock.

The clock divider is a division of the CLKIN prior to or imbedded in the SERDES PLL (not shown in the block diagram). 

The clock divider can be set to divide-by-2 or divide-by-4 (Register 53, bit 7)

The SERDES PLL provides a 10x or 20x  multiplication (40x mode is not shown in the block diagram).  Probably because the divide-by-2 or 4 is inside the SERDES PLL block I am guessing?

For the Mode 0 (LMF = 484 case), the CLKIN frequency max = 500 MHz.  In this case, the SERDES bit rate is 10 Gbps. 

The PLL mode = 40x.  Is the 40x interpreted as the multiply of CLKIN/2 rate to the SERDES bit rate? 

Is this interpretation correct?  I just want to understand the 40x mode definition from both the JESD mode and JESD PLL mode. 

It seems that the actual JESD PLL definition is 20x mode with divide-by-2.  What specifically is the 40x mode internally providing?

Thanks,

Troy Robinson

  • 0
    TI__Expert 3895 points
    Hi Troy,
    I'll see if I can help here.
    In mode 0, the ADC sampling clock is 500Msps. Internally we have 2 ADCs (@ 250Msps) interleaved to 500Msps so the internal core clock rate is 250Msps. That's where the 40x PLL clock multiplier comes from.
    In mode 0, you get 2x complex decimation so the output rate is 250Msps complex. With 8b/10b JESD204b encoding you effectively transmit 10Gbps (2x 250Msps x 16bx 10/8) on one lane per channel. This mode gives effectively same output as the bypass mode.
    BTW another option to consider is the ADS54J64 which is also 4ch and similar power. However it uses an extra 2x clock with additional internal 2x LPF decimation. This basically doubles the Nyquist zone from 250MHz to 500MHz which allows much better frequency planning. The ADS54J66 was designed to give high SFDR over ~ 100MHz BW while the ADS54J64 enables 200MHz BW.
  • 0 in reply to Thomas Neu
    Prodigy 80 points
    Thanks for the clarification. The block diagram for the ADS54J64 shows the divide-by-2/4 and helps me now that I understand that sampling is performed with multiplexed ADC at 1/2 CLKIN frequency. With the ADS54J66, using complex spectrum, we obtain a 250 MHz complex BW, which is sufficient for us. I can request pricing on the ADS54J64 with our inside TI sales guy to see if it is a viable option too. Just a minor detail, but the block diagram in both the ADS54J64 and ADS54J66 should show 20x/40x in the SERDES PLL (not 10x/20x as is shown) because those are the real effective multiplication factors needed in the SERDES PLL after the divide-by-2/4. It just caused me some confusion, but after explanation, you help clear it up for me.
  • 0 in reply to Troy Robinson
    TI__Expert 3895 points
    Hi Troy. Thanks for the feedback. Please let us know if there is anything else we can help with.
    Tommy
  • 0 in reply to Troy Robinson
    Prodigy 80 points
    I am looking through the serial programming of the ADS54J66 and I am confused when the "P" bit in the serial word is to be set. What does page access provide that register access does not. I see in the examples that to set the address 0x03 and 0x04 registers the "P" bit is generally set to a '1'. When the always 1 bits at address 0x39 in the master page is accessed with P='0'. Can the "P" bit be explained to describe when it is necessary and when it is not?
    Thanks,
    Troy
  • 0 in reply to Troy Robinson
    TI__Expert 3895 points
    Hello Troy. The 'P' bit is used to distinguish between selecting the digital page and writing register content into the digital page.
    P=0 is used to select one of the digital pages (main digital, interleaving engine, JESD digital, JESD analog and decimation filter).
    P=1 is used to write register content.

    So in digital writes 400xh is selecting the page, 60xxh is writing register content.
    Here is an example to illustrate from data sheet page 29 (writing FOVR config):
    4004h, 68h: access main digital page
    60ABh, 01h: enable bit D0 overwrite