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DAC8565: Interfacing with ESP32

Christiaan Muller
Prodigy 50 points
Part Number: DAC8565

Hi,

I seem to have problems interfacing the DAC8565 using my ESP32. Using a multimeter I measure 3.2V at all 4 outputs constantly, though in my code I try to change between 2 voltages: https://gist.github.com/ChristiaanMuller/b1622f646d676a077ff5781c65003dd6.

LDAC, ENABLE, RSTSEL connected to GND

I've connected the DAC8565 like this:

ESP32 -> DAC8565

IO5 (SS) -> 9, SYNC
IO18 (SCK) -> 10, SCLK
IO23 (MOSI) -> 11, DIN
IO15 (RST) -> 13, RST
GND -> LDAC, ENABLE, RSTSEL, GND
3V3 -> AVDD, IOVDD,VREFL

Would be amazing if someone can help me out. 

  • 0
    TI__Mastermind 46290 points
    Christiaan,

    Can you please share a complete schematic for this design? The pin connection listing you have provided in lieu of a schematic is missing a description of the VREFH connection, which is critical for understanding the configuration of the DAC.

    You have VREFL connected to 3.3V, according to your listing. If this is an accurate connection and not a typo, then this is the root cause of your problem.
  • 0 in reply to Kevin Duke
    Prodigy 50 points

    Hi Kevin,

    Many thanks for your reply. This is a quick schematic of my connections: 

    https://ibb.co/hOQXNn

    VREFout is not yet connected, in the future will be provide a reference voltage for OPA's.

    I've indeed connected VREFL to 3.3V as I thought it's necessary to provide a reference voltage for the DAC. I'm not sure how to connected it differently?

    If I look at this example: https://github.com/mxmxmx/O_C/blob/master/hardware/o_c_rev2e_schematic.pdf, VREFL is connected to both GND and 3.3V via a capacitor, is this the way to do it?

  • 0 in reply to Christiaan Muller
    Prodigy 50 points
    Just a quick message inbetween. I've tried connecting VREF to GND, but still no progress unfortunately..
  • 0 in reply to Christiaan Muller
    TI__Mastermind 46290 points

    Christiaan,

    By default the device has an internal 2.5V reference which is enabled and available on the VREFH / VREFOUT pin. By the sounds of your follow-up posts, you are planning on using this internal reference. In such a case, VREFL should be connected to GND. Really, in all cases VREFL should be connected to ground maybe +/-0.3V as the intention of this connection was really only small compensation. If VREFL is biased with too high of a voltage there will be some issues with the biasing of the internal switches - this should be documented more clearly in the PDS in my opinion...

    I suspect that by having 3.3V connected to VREFL with the internal reference enabled, some internal circuits may have been damaged since VREFL > VREFH.

    Equation 1 on Page 25 of the datasheet defines VOUT in terms of VREFH, VREFL, and DIN. You'll notice that with 3.3V VREFL, the internal reference, and with 3.3V AVDD the output will always be railed out regardless of what the input code is.

    I'll also point out that there appears to be an error in this equation as the "2x" should not really be there since, per Figure 93 and typical implementations of String DACs, the lead resistor in the string divides the reference by 2, so even though the output stage has gain 2 the overall equation should not have any leading coefficient.

    Christiaan Muller said:
    Just a quick message inbetween. I've tried connecting VREF to GND, but still no progress unfortunately..

    Not sure if this is in reference to VREFL or VREFH. I suggest you try your setup again with VREFL connected to GND on a fresh unit since I suspect there has been some damage with such a large potential on VREFL versus AVDD / VREFH.

  • 0 in reply to Christiaan Muller
    TI__Mastermind 46290 points

    Christiaan Muller said:
    If I look at this example: https://github.com/mxmxmx/O_C/blob/master/hardware/o_c_rev2e_schematic.pdf, VREFL is connected to both GND and 3.3V via a capacitor, is this the way to do it?

    Though it appears that VREF_L is being connected to both GND and 3.3V that's not really the case - this is just some misleading drafting. VREF_L is connected to GND. AVDD has a 100nF decoupling capacitor from the 3V3_A net. It is very typical for analog components to include bypass capacitors on the supply lines.

  • 0 in reply to Kevin Duke
    Prodigy 50 points
    Kevin, many thanks for having a thorough look into this. I suspect I have indeed damaged the unit by connecting VREF_L to 3.3v. Unfortunately I haven't got another one at the moment, but ordered a few on mouser, which will take a few days. Will keep you up-to-date. Also will have a look with a logic analyzer what i'm actually outputting on the SPI channels. Will be posting if it doesn't work out, if it will also. Thanks again, appreciate this!
  • 0 in reply to Christiaan Muller
    TI__Mastermind 46290 points
    Christiaan,

    Sounds good - please keep us posted.
  • 0 in reply to Kevin Duke
    Prodigy 50 points

    Hi Kevin,

    I finally got the DAC to work. 
    I hooked up an Arduino Teensy 3.2 and it worked on this one. Strange. Why?
    I looked at the difference between using an ESP32 running Arduino code and the Teensy and identified that I was using long breadboard cables for the ESP32. When I changed the MOSI cable to be a short one, the chip worked perfectly. Seems to be just a breadboard prototyping issue!

  • 0 in reply to Christiaan Muller
    TI__Mastermind 46290 points
    Christiaan,

    That is great news and I am glad that you have your system working!

    Please come back and let us know if there is anything else we can help you with.
  • 0 in reply to Christiaan Muller
    Prodigy 10 points
    Hi,

    I have tried to use yor code (same connections on a breadboard), it didn't work. Then I have changed to SPI_MODE2 (from SPI_MODE0), and it worked !!!

    regards,
    Victor.
  • 0 in reply to Victor Joco
    TI__Mastermind 46290 points
    Victor,

    Thanks for sharing. I did not look at the code myself - generally I prefer to see the outcome on the bus as a primarily analog engineer, but that looks to be correct. I've not used Arduino at all so my definitions may be a bit off but the DAC datasheet describes a falling edge as the read edge via timing specifications t5 and t6. They are each measured against the falling edge of SCLK.

    Looking at some Google resources it looks like SPI_MODE0 is CPOL = 0 and CPHA = 0, which would capture data on the rising edge. Meanwhile SPI_MODE2 is CPOL = 1 and CPHA = 0, which captures data on the falling edge (aligned with the datasheet). You could also use SPI_MODE1 with CPOL = 0 and CPHA = 1 if you didn't want the clock to idle high all the time.

    Thanks again, Victor!