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ADC32RF45: ADC32RF45

E G
Intellectual 400 points

Part Number: ADC32RF45

Hi,

I am using ADC32RF45 in LFMS=82820 mode. I am only using channel A. I am kind of confused with the number of lanes I should be using. in LFMS since L=8 am I supposed to use 8 lanes or 4 lanes? When I implemented a JESD IP core on FPGA side with 4 lanes and checked the ILA configuration data that comes to FPGA from ADC I see number of lanes required for link is 8. When I also cheked the lane IDs of the lanes in use I see numbers 4 to 7.  I only connected 4 lanes since I am only using ChA. Am I doing anything wrong? This mode of operation seems confusing to me. If I'd like to use ADC32RF45 CHA only in LFMS=82820 mode should be using all 8 lanes or only 4 lanes?

Erdal

  • 0
    TI__Guru* 91947 points

    E.G.,

    If you plan on using 12 bit bypass mode, the only option available for the ADC is with LMFS = 82820. Since the FPGA controls the function of SYNC, it is possible for this mode to work with only four lanes if you only plan on using only CHA. The FPGA will monitor the four lanes from CHA, and once the CGS has passed, it will de-assert the SYNC signal and the ADC will start sending data out on all 8 lanes.

    Regards,

    Jim  

  • 0 in reply to jim s
    Intellectual 400 points

    Hi Jim,

    Thanks for the quick response. In my case FPGA asserts sync (sync ='1') and then ADC starts sending ILAS and real data. In your answer above you said after CGS ADC will start sending data on all 8 lanes. Still, I will be using the data on the first 4 lanes (DA0-DA3) only, right? Because I need data from CHA only.

    Erdal

  • 0 in reply to E G
    TI__Guru* 91947 points

    Erdal,

    That is correct. In your case you will power down CHB with a register write so the data on the other 4 lanes will be invalid.

    Regards,

    Jim