TSW54J60EVM: JESD interface error

Hi mallesh
We are looking into your questions. Someone will respond soon.
Can you let us know what configuration settings you are using with the TSW54J60EVM?
Are you using TI provided example firmware for the Xilinx FPGA board, or is it firmware you have developed independently?
Best regards,
Jim B

Mallesh,

What Xilinx board are you using? What errors are you getting? Try this sequence:

1. Power up the TSW54J60EVM and FPGA board.

2. Get the clocks programmed on the TSW54J60EVM.

3. Press the ADC board reset switch.

4. Program the ADC.

3. Configure the FPGA.

Regards,

Jim

 

I am using TI provided example code as a baseline. I have only added rtl to further process the samples. But everything else remains the same.

This configuration is same as the one in user guide.
My TSW54J60 configuration is as follows:

1. Clock is set to 983.04 MHz.
2. JESD lane configuration is 8224(LMFS).
3. No decimation.

void JESD_config(void)
{

JESD204_write( RX_SCRAMBL_REG, 0x0 );
JESD204_write( RX_F_REG, 0x1 );
JESD204_write( RX_K_REG, 0xf );
JESD204_write( RX_LANES_REG, 0xff );
JESD204_write( RX_ERR_REP_REG, 0x1);
//JESD204_write( RX_RESET_REG, 0x1 );
//delay(10);
//JESD204_write( RX_RESET_REG, 0x0 );
}

Please let me know if you need any more information.

Thanks.

Mallesh

Jim,

I am using genesis 2 board.

store.digilentinc.com/.../

Yes with the above sequence it works most of the time. Failure rate is once in 5 times or so.

But if I change the sequence as follows.

1. Power up the TSW54J60EVM and FPGA board.

2. Get the clocks programmed on the TSW54J60EVM.

3. Press the ADC board reset switch.

4. Program the ADC.

5. Configure the FPGA. --> it is working.(most of the time works).

6. Power cycle FPGA board.

7. configure FPGA board -> some times works sometimes does not.

Mallesh

Mallesh,

Without knowing the error, it is hard to help you. Have you consulted with the FPGA vendor? Is the FPGA not asserting and de-asserting SYNC properly? Are you using the LMK on the TSW54J60 to provide the device clock and SYSREF to the FPGA? These signals are normally driven as LVDS out of the TSW54J60. Is this what the FPGA is expecting? Is your K value the same on both ends? Double check the ref clock frequency required by the FPGA and what is sent by the TSW54J60 to make sure it is at the correct frequency. Is the FPGA driving SYNC as a LVDS signal to the TSW54J60?

Regards,

Jim 

Jim,

Thanks for your help.

Is the FPGA not asserting and de-asserting SYNC properly?

-> I will check this.

Are you using the LMK on the TSW54J60 to provide the device clock and SYSREF to the FPGA?
-> Yes. I am using LMK

These signals are normally driven as LVDS out of the TSW54J60. Is this what the FPGA is expecting? Is your K value the same on both ends?
-> Yes. This is configured correctly.

Double check the ref clock frequency required by the FPGA and what is sent by the TSW54J60 to make sure it is at the correct frequency. Is the FPGA driving SYNC as a LVDS signal to the TSW54J60?
-> I will check this.

I had not enabled scrambler. I will enable that. Probably it will help.

Mallesh

Mallesh,
How are you proceeding with this?
Regards,
Jim

Hello Jim,

I have not worked on it. I will let you know as soon as I make some more progress.

Mallesh