DAC5681Z: issue with Register Programming

Hi Madan
We are reviewing your questions. Someone will respond soon.
Best regards,
Jim B

Hi Madan,

Did you follow Initialization set-up? As show in section 7.3.16 of the datasheet?

7.3.16 Initialization Set-Up
7.3.16.1 Recommended Start-Up Sequence
The following start-up sequence is recommended to initialize the DAC5681Z:
1. Supply all 1.8-V (CLKVDD, DVDD, VFUSE) voltages simultaneously followed by all 3.3-V (AVDD and
IOVDD) voltages.
2. Provide stable CLKIN/C clock.
3. Toggle RESETB pin for a minimum 25-nSec active low pulse width.
4. Program all desired SIF registers. Set DLL_Restart bit during this write cycle. The CONFIG10 register value
should match the corresponding DCLKP/N frequency range in the Electrical Characteristics – Digital
Specifications table.
5. Provide stable DCLKP/N clock. (This can also be provided earlier in the sequence)
6. Clear the DLL_Restart bit when the DCLKP/N clock is expected to be stable.
7. Verify the status of DLL_Lock and repeat until set to 1. DLL_Lock can be monitored by reading the
STATUS0 register or by monitoring the SDO pin in 3-wire SIF mode. (See CONFIG14 SDO_func_sel.)
8. Enable transmit of data by asserting the LVDS SYNCP/N input or setting CONFIG3 SW_sync bit. (See
CONFIG3 SW_sync and CONFIG3 SW_sync_sel.) The SYNC source must be held at a logic 1 to enable
data flow through the DAC. If multiple DAC devices require synchronization, refer to the Recommended
Multi-DAC Synchronization Procedure.
9. Provide data flow to LVDS D[15:0]P/N pins. If using the LVDS SYNCP/N input, data can be input
simultaneous with the logic 1 transition of SYNCP/N.

Regards,
Neeraj Gill

I followed initialization steps as specified above,
But problem I am facing is If I program config03 register as ox70/73 ,I am not able to get output but If I don't program that register I am getting required output

Hi Madan,

Are you using the DAC5681Z EVM or is it your board?

Do you have external sync signal? Or are using the SW sync?

if you are using SW_SYNC try setting Config3 to 0x71 and in the very end set it to 0x73.

Regards,

Neeraj

Hi Madan,

Were you able to get the board up and running?

Regards,
Neeraj

we are using our own board (not EVM)
we have external sync signal
I am able to get output waveform but the problem is when I change the sequence of register programming output changes( like reduction in output level and increase in noise floor)

Hi Madan,

Since you are using external sync signal. You don't really need to use SW_SYNC you can just set config3 to 0x70.

Regards,
Neeraj Gill

The problem is if I program that register I am getting random waveform,if I don't program that register I am able to get output, I don't know for what reason

Hi Madan,

Can you send me the screenshot of the waveform?

Regards,

Neeraj