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JESD204B over fiber

aronii
Expert 1140 points

I was wondering if TI JESD204B converters embed the clock/sync in the data stream?

I would like to transfer the JESD204B data from the ADC over one fiber and then send it to a JESD204B DAC and reconstruct the Analog data.

Is it possible to do that using TI's data converters? I mean without a FPGA .

Just ADC + clock source + Analog front end on one side and a DAC + Clock + Analog front end on the other side.

 Is there any reference design for it?

I am looking for 14 bits + converters sampling at 200MHz minimum.

  • 0
    TI__Mastermind 44680 points

    Hi aronii

    It is possible to send JESD204B over fiber optic links, but we haven't done any work to directly couple ADCs to DACs without an FPGA.

    Please take a look at this Analog Applications Journal article on this subject:

    http://www.ti.com/general/docs/lit/getliterature.tsp?baseLiteratureNumber=slyt663

    Here is a video showing the platform:

    http://www.ti.com/general/docs/video/watch.tsp?entryid=drupal:7.x:3980:31d555187c3bc08a5dc0003ac675c200&keyMatch=ims2015%20joos&tisearch=Search--Everything

    Best regards,

    Jim B

  • 0 in reply to Jim Brinkhurst1
    Expert 1140 points

    Jim,

    Sending the JESD204B signals over few fibers + additional fiber/s for synchronization is not a cost effective way to transfer such signals.

    I hope that you know how much would those optical transceivers cost + additional cost of so many fibers and it becomes quite expensive.

    In that case, there is no advantage to use JESD204B converters (the "constant latency" can also be achieved with standard ADCs + FPGAs). Using a $50 FPGA + only 1 transceiver (at 10 or 20 Gb/sec) cost less.

    The reason that I asked this question is because I saw that movie from Intersil:

    If you watch that movie, you would see that they use a single fiber (the orange one). They explain that the SYNC signals are already embedded in the JESD204B data stream and therefore they don't need additional fibers for synchronization.

    If you will watch that movie slowly, you would notice that the 2 signals to the optics board comes directly from the ADC board. The FPGA board there is actually a clock generator. It has nothing to do with the transmission of the JESD204B signal.

    I wonder if TI got an ADC with embedded sync as presented on that movie? This embedded SYNC would eliminate the need for an additional fiber/s.

  • 0 in reply to aronii
    TI__Mastermind 44680 points

    Hi

    I reviewed the referenced video and have several comments about the demo in the video and the requirements of JESD204B in general.

    ~SYNC:

    ~SYNC is an upstream signal from data receiver to transmitter. It is used during link initialization to control the transmitting device through the CDR (clock data recovery) and ILA (initial lane alignment) steps. In the referenced demo they are controlling the SYNC function of the transmitter through an SPI register bit. I'm not sure how they are coordinating the needs of their data receiving FPGA with the SPI writes but they must be doing that do some degree, using a path outside the optical link. It is clear that they are not sending SYNC through the optical link (this would require a link from the receiving FPGA or DAC upstream to the ADC). Some the TI converters also support register control of the SYNC function, but this control will need to be coordinated from the data receiver to ensure proper link startup.

    Clocks:

    While the data clock is technically embedded in the serialized data stream, JESD204B devices require at least 1 and usually 2 different clock signals that must be frequency and/or phase locked at TX and RX ends of the link. To achieve synchronization between multiple data generators and receives as shown in the JOOS demo, the ADCs, DACs and FPGAs all must receive Device Clocks and SYSREF. The Device Clock signals are used for generation of the ADC and DAC sample timing. The SYSREF signals are used to synchronize the LMFC (local multi-frame clocks) which align the data frames in all TX and RX devices.

    In the TI JOOS demo SYSREF timing information is sent over an optical link so that synchronized Device Clocks and SYSREF signals can be generated locally at the TX and RX ends of the links.

    If multi-converter synchronization or deterministic latency are not required then SYSREF may be optional for some devices. Several of the TI ADC products can operate without SYSREF in these scenarios.

    DATA:

    In the video you linked above, the 12-bit 145MSPS converter data can be sent over a single 4.375Gbps JESD204B link which is sent over one optical link.

    It is possible to aggregate multiple JESD204B lanes into a single optical link. This is done in the JOOS demo, where multiple 10Gbps channels from the ADCs and for the DACs are combined and sent over a single optical link. The optical transceivers used support 12 differential channels at 10 Gbps in each direction. This allows 6 ADC channels and 6 DAC channels to share a single optical TX/RX link.

    Additional information on JESD204B capabilities, requirements and implementation details can be found at the following link:

    https://training.ti.com/high-speed-signal-chain-university

    Best regards,

    Jim B