Dears.
The customer board was designed in ADC32RF80.
The setting values are as follows.
L: 4
M : 4
F : 2
C : 1
K : 32
Scramble : Off
Sampling : 3Ghz
Serdesclk : 250M
Jesdcore clk : 125M
sysref : 7.8125M
The data output from the ADC32RF80 is captured in the FPGA as follows.
What is the solution?
Thank you.
