ADS7049-Q1: Delay time: SCLK falling to data valid on DOUT Max. 25ns. Is there a low limit?

Part Number: ADS7049-Q1

Hello,

In the data sheet it mentions that SCLK falling to data valid on DOUT is MAX. 25ns. This uncertainty would cause trouble for reading in the data at controller side when SCLK speed is >= 20MHz (setup and hold timing). Is there a low limit for this value? Or delay needs to be implemented at controller side to guarantee the timing requirements? Thanks.

Wang,

Welcome to the TI E2E Forum!!

You are right. Data is launched by the ADS7049-Q1 on the fall edge of the SCLK and, typically, the controller is expected to capture this on the subsequent rise edge. But with a SCLK to DOUT delay of 25ns, the data may not be available in time for the rise edge.

There are two ways to workaround this incase of faster SCLKs.

1. Implement a delay on the controller, as you mentioned.

2. Treat the SPI as a full cycle interface - with data captured on the next fall edge of the SCLK.

Hope this help.

Regards,
Sandeep