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DAC38RF82EVM: JESD204B Frame format for for LMFSHd = 82380

Tong Xu
Intellectual 515 points
Part Number: DAC38RF82EVM
Other Parts Discussed in Thread: DAC38RF82, ADC12J4000EVM

Hi Everyone,

I'm trying to interface DAC38RF82EVM with a FPGA board. I already finished a project which uses single (8bits) DAC with a sampling rate of 9GSPS.

Now I want to configure the DAC to operate in dual (12bits) DAC mode. I checked the datasheet of DAC38RF82 and found a table as follows:

In my understanding, the i corresponds to DAC A and q corresponds to DAC B, and each of them has 12bits. 

However, the JESD204B core in Vivado only accepts 32bits input in each JESD lane which is not divisable by 12. Can anyone tell how to arrange the data in JESD frame?

I also noticed that the JESD serial lane rate is 11250MHz if I set the DAC to operate in 3GPS, dual channel mode and 12bits resolution. Does this mean the JESD core clock is 11250MHz/40 = 281.25MHz? If this is true, each DAC will receive 3000/281.25 = 10.6667 samples during a FPGA clock cycle, which is not an integer. Is there anything wrong in my understanding?

Thank you.

  • 0
    TI__Genius 9695 points
    Hi Tong,

    The data resolution is 12bits but you can move 32bits of this data to the JESD204B input in FPGA on each active edge of fpga clock. It will not be a whole number of samples but that is ok, the DAC will accumulate 96bits (or 8 12bit samples) before processing the data.

    Thanks,
    Eben.
  • 0 in reply to Ebenezer Dwobeng
    Intellectual 515 points
    Hi Eben,

    Thanks for your answer.

    I guess my understanding is correct. However, in this case the number of samples being sent to DAC in each FPGA clock cycle is not an integer. Does this mean the parallel processing in FPGA is very difficult to manage? Is the I/Q input instead of real input a more preferable way to use the DAC?

    I also have similar problem when using ADC12J4000EVM in bypass mode, since the resolution is 12bits while each JESD IP core requires 32bits input for each lane.

    Regards,
    Tong
  • 0 in reply to Tong Xu
    TI__Genius 9695 points
    Hi Tong,

    We do not require you to send an integer number of samples in every clock cycle when using 12bits mode. Maybe it is better if you think of the data transfer in terms of octets and not samples. 1 octet = 8bits and the JESD204B IP requires 4 octets=32bits per lane in every clock cycle so I think it should not be difficult to provide 4 octets from your data every clock cycle.

    Thanks,
    Eben.
  • 0 in reply to Ebenezer Dwobeng
    Intellectual 515 points

    Hi Eben,

    Thank you very much.

    I understand what you are saying. It's not difficult to send 4 octets to JESD204B lane in each FPGA clock cycle.

    Suppose the sampling rate of DAC is 3GSPS without interpolation, then the FPGA clock frequency would be 281.25MHz. In this case, the DAC receives 3000/281.25 = 32/3 samples in every FPGA clock cycle. It's easy to split every two 12bits samples into three octects and provide 4 octets to a JESD204B lane in every clock cycle.

    But I still feel it's difficult to manage the data stream if I want to do parallel processing (such as filtering, up/ down conversion) for the data, since the number of parallel channels is not an integer in this scenario. Is there any convenient way to process the data?


    Regards,
    Tong

  • 0 in reply to Tong Xu
    TI__Genius 9695 points
    Hi Tong,

    Unfortunately, I do not have any recommendation for handling the data parallel processing you describe above.

    Thanks,
    Eben.