This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DDC264EVM: Related to DDC264EVM schematic

Part Number: DDC264EVM

I have two doubts

1. Why 47k resistors are connected at Din_cfg and Reset pins  in DDC264EVM

2. Why RC filter is connected to CLk ,Dclk and Conv pins in DDC264EVM

  • Hi Sebin,

    Regarding your questions on the DDC264EVM,

    1. DIN_CFG and RESETn signals are pulled down to GND through 47k to ensure the signals are held low during power up and until the FPGA / controller configures the device.

    2. The RC network acts as a low pass filter on these signals and to suppress any EMI. The design is very conservative and may not possibly be needed in your design.
  • Hi Sebin,

    I am closing this post. If you have any further questions, feel free to start a new thread.