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ADS1282: Time to first conversion result

starryfree
Prodigy 110 points
Part Number: ADS1282

Hi,TI

      I have a question about ADS1282:

1.From CPU send a collect instructions, to received the first simple, the time spent is a constant value, or a non fixed value?

2.If the time is a constant value,what is the value? or how to test the value?

3.If the time is not a constant value,is it have a value range?and how to test the value?

Best regards,

  • 0
    TI__Mastermind 44680 points
    Hi starryfree,

    I can help answer your questions...

    When you start an ADC conversion, there will be a very determinate time between the beginning of the conversion to when /DRDY goes low. There is some timing information about this shown in table 10 of the ADS1282 datasheet. The exact time will depend on the configured data rate, and the fclk frequency that you are providing to the ADS1282.

    Please note that the RDATA command doesn't start the conversion process, but only helps in clocking out the data after the conversion has completed. To begin conversions, make sure sure the CLK is applied and set the /PWDN, /RESET, and /SYNC pins high.

    Best regards,
    Chris
  • 0 in reply to Christopher Hall
    Prodigy 110 points

    Hi,Christopher Hall

         Thank you very much for your reply, and now I have another question.

         Set to the sampling interval is 1ms, collecting 60000 samples to save a txt document.

         We send instructions, start the acquisition, the time stamp of first simple received marking as the file name，such as 20180326_181629_00000000.Normally, the time stamp of the next documents should be 20180326_181729_00000000 (eg.1ms x 60000=1minute), But the actual test result is 20180326_181729_00000526.

         The following is continuous acquisitio 30 minutes：

    20180326_181629_00000000

    20180326_181729_00000526

    20180326_181829_00001052

    20180326_181929_00001580

    20180326_182029_00002106

    20180326_182129_00002631

          So, the latter file's time stamp has more 500us than the previous file......

    Question 1: what is the possible cause of the time stamp difference?
    Question 2: what will be happened if SPI CLK frequency > 2.048MHz?

  • 0 in reply to Christopher Hall
    Prodigy 110 points

    Hi,Christopher Hall 

          Thank you for your reply!

          If I set th ADS1282 sampling interval is 1ms, acquisit data 60000,Is the time actual spent  1 minutes or more than 1 minutes? How should I calculate the time spent?

  • 0 in reply to starryfree
    TI__Mastermind 44680 points

    Hi starryfree,

    I'm not sure I fully understand your hardware setup and where the extra 500us is coming from. There are two possible delays that I would think need to be considered...

    1. When starting an ADC conversion, the first settled conversion result occurs on the ~63rd conversion cycle. You can think of the FIR filter as having 63 taps such that the filter output calculation is only accurate after collecting 63 conversion results. If you restart the ADC conversions between samples or between data sets (files) you'll have this delay included in the time stamp.

    2. How much hardware delay is there between the ADC SPI interface and your PC? Is the data from the ADS1282 going to an MCU and then transmitted to the PC over USB? If so, there will be some interface delays associated with the SPI and USB interfaces. The USB interface delay might not be the most consistent as your operating system generally schedules and prioritizes which devices can utilize the USB bus and when.

    Regarding the ADC clock, changing the clock frequency will change the effective data rate of the ADC. All of the data rates listed in the ADS1282 datasheet are with respect to a nominal 4.096 MHz clock.

    Best regards,
    Chris

  • 0 in reply to Christopher Hall
    Prodigy 110 points

    Hi,Christopher Hall

    This problem has been solved, thank you very much for your support!

    Best regards

  • 0 in reply to Christopher Hall
    Prodigy 110 points

    Hi,Christopher Hall

    When you start an ADC conversion, there will be a very determinate time between the beginning of the conversion to when /DRDY goes low. There is some timing information about this shown in table 10 of the ADS1282 datasheet. The exact time will depend on the configured data rate, and the fclk frequency that you are providing to the ADS1282.

    Do you means if fDATA=1000,fCLK=4.096M,the time form send the command to recevied the first simple is 62.98046875/1000 + 468/4096000=0.6299s?

    Best regards!

  • 0 in reply to starryfree
    TI__Mastermind 44680 points

    Hi starryfree,

    That is correct! That equation applies to the FIR filter, and the equation in Table 35 applies to the SINC filter.

    Therefore, if you being (restart) the ADC conversions you should see /DRDY go low after that time. If you are not monitoring /DRDY, then you can approximate when the data conversion has completed. I say "approximate" because you might need to account for clock frequency errors.

    Best regards,
    Chris

  • 0 in reply to Christopher Hall
    Prodigy 110 points

    Hi,Christopher Hall 

    Thank you for your help!

    Best regards!