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ADS7953: Reduce interface pin count by connecting one CLK and/or SDI and/SDO to multiple ADCs

Hans van de Laar
Prodigy 130 points
Part Number: ADS7953

For added diagnostic on a PCBA I like to add several ADS7953 (15pcs).

Is it possible to reduce the interface pin count to the controller (FPGA). For example connect all CLK lines, SDI and SDO lines to three FPGA pins and 15 CS selections pins. This would reduce the pin count on the FPGA from 60 to 18.

A sample rate of 1Hz for each input is enough for diagnostics purposes.

Taking SI in to consideration: one bus line, no/short stubs to the ADCs pins.

  • 0
    TI__Expert 4405 points

    Hello Hans,

    Welcome to the TI E2E Forum !!!

    It is possible to implement the interface as you have described. The tri-state capability on SDO was included to enable exactly such a scenario. However, you should carefully consider signal integrity and fanout requirements on IOs both at both the host and device end.

    With 15 devices connected on a single board the SCLK, SDI and SDO signals could end up with have significant trace lengths (and associated capacitance) and several stubs. Careful placement and routing will help.

    Most FPGA allow drive strength control on their IOs and it should be possible to optimize the drive on CS, SCLK, SDI.

    For SDO, ideally I should recommend that you download the IBIS model for this family and simulate the expected behavior. But since you intent is to operate at 1Hz per channel, my hunch is that you have all the time in the world to run the interface at a really slow speeds to ensure that the signals reach their correct VIH/VIL levels before they are sampled. If you have a few FPGA IOs to spare, I would recommend grouping the SDOs in 3 or 5 per FPGA input to reduce the load. This would enable you to run the interface (5 or 3 times) faster, if you choose to in the future.

    Regards,

    Sandeep