This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

ADS1292R: ADS1292 Lead-off detect abnormality

Part Number: ADS1292R
Other Parts Discussed in Thread: ADS1292,

Hi:

   We have a device use the ADS1292 chip, we can read the ADC data correctly via the SPI bus when Lead wire is connected。

   But we found the lead-off detect is invalid when the lead wires is disconnected, the state of register is unchanged.  How can I get the correct state for lead-off detect?

   The state of status register read after lead wires connected or disconnected show below:

                                                            CH1                              CH2    

                                                         P        N                      P            N

  Lead wire disconnect                     0         1                      0             1

  Lead wire connect                          0         1                      0             1

                             0-->connected; 1-->disconnected.

      The ADS129's registers  configure as below:   

unsigned char ADS1292_Default_Register_Settings[12] = {
//Device ID read Ony
0x00,
//CONFIG1
0x02,
//CONFIG2
0xE0,
//LOFF
0x10,
//CH1SET (PGA gain = 6)
0x00,
//CH2SET (PGA gain = 6)
0x00,
//RLD_SENS (default)
0x20,
//LOFF_SENS (default)
0x3F, 
//LOFF_STAT
0x00,
//RESP1
0x02,
//RESP2
0x07,
//GPIO
0x0C 
};

  • Hello Zhirong,

    Welcome to our forum, and thanks for your post!

    Can you please provide a schematic of your ADS1292R circuit?

    You might also try increasing the LOFF current magnitude or lowering the comparator thresholds to see if lead-off is detected more frequently.

    Is there a reason you have flipped the current source direction on both channels?

    Best Regards,
  • Hi Ryan Andrews:

        We have tried to reduce the comparator threshold(Comparator positive side  70% and Comparator negative side  30% in LOFF: Lead-Off Control Register ), and this approach is invalid when the LOFF current magnitude is fixed to 6nA.

        When the comparison threshold is constant (Comparator positive side  95% and Comparator negative side  5% in LOFF: Lead-Off Control Register), increase the  LOFF current magnitude to 6uA, the lead-off is effective;but the ECG signal is too poor to be recognized. When the lead line is not connected, the read value is 0x80000. When the lead line is connected, the read value is mostly noise, not the normal ECG signal.

    BRs

    Wu, Zhi-Rong

  • Hi Ryan,

    The figure as below is the schematic of our ADS1292R circuit, Thank you.

  • Hi Rex,

    Thanks for sharing the schematic. A couple things you can try to improve the design:

    1. Split the series 51k on each input to 22.1k and 10k, each followed by a common-mode cap (i.e. 47 pF). This will give you a second pole in your anti-aliasing filter.
    2. Consider adding a 470 pF differential cap between INxP and INxN. This will reduce the overall frequency response to ~3.3 kHz, which is more than enough for ECG, and may help remove more of the input noise. A differential cap is also better for CMRR.

    What is the input signal source? I would recommend testing with a function generator or patient simulator as a reliable input signal for comparison. Alternatively, you can short the input connections together (ELA_PAD with ERA_PAD and ELA_LEAD with ERA_LEAD) and analyze the RMS noise for each channel. I don't expect the noise to increase significantly with the differential lead-off current magnitudes.

    Best Regards,

  • Hi Ryan,

    Thanks for your suggestion and we'll test it. I have another question Is that fine we change Rp(R36) to 1.1K improving the CMRR & noise? Is there any side effect? 

    BR
    Rex

  • Hi Ryan,
    We have some questions as below.
    1.Is that available if Rp(R36) is set 30K ohm? And how low of Rp of the resistance can be set?
    2.In our schemetic, Cf and Rf are 1M and 1.5nF, could we change Cf and Rf to 2.2M and 680pF? Is there any side effect?

    Becasue we want to improve our CMRR or you could give us some suggestion.

    Thank you.

    BR
    Rex
  • Hi Rex,

    I don't see any problem with changing the Rf and Cf values as you proposed above. The DC gain of the RLD loop is set by Rf / (220k || 220k || ...), depending on the number of PGA outputs selected for RLD common-mode derivation. Increasing Rf will increase the closed-loop gain and output a larger common-mode cancellation signal.

    Rp can be reduced and should improve CMRR slightly, but you must have enough impedance to limit the DC current in the case of a fault. Please see Table 1 in sbaa188 for a summary of CMRR results with different Rp values.

    Best Regards,