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CDCE62005 CLK Driver for ADS5463

LeonardEllis
Guru 71526 points
Other Parts Discussed in Thread: CDC7005, CDCE72010, ADS54RF63, CDCE62005, ADS5463, CDCM7005

Engineer is wanting to use the CDCE62005 as the CLK driver for the ADS5463 (or ADS54RF63) even though I have tried to direct them to the CDCE72010 or CDC7005.  He is wanting to know the specific termination scheme for this interconnect.  The App Notes give choices, from AC-coupled xfrmr to direct connection. 

Do we have a ref design for this combination of '62005 to ADS5463?  And one for the CDC7005 to the ADS5463?  What advantage/disadvantage of each for this ADC?

-Leonard

 

  • 0
    TI__Expert 6040 points

    Leonard,

       We don't have 62005 to ADS5463 ref design, but I can check out CDC7005 for you, because we have done some work on CDC7005. For how to use 62005 and termination requirement for 62005 please ask 62005 device group to get the best support. You can tell them ADS5463 clock input has 2 kohm differential resistance and 0.75pf cap differentially, 2.4v comm-mode voltage provided internally, I would suggest to use AC coupling on the clock path. I will copy this case to 62005 device group in E2E.

    Regards,

    Hui Qing

     

  • 0
    TI__Mastermind 18095 points

    One additional note.  The CDC62005 jitter performance (~660 fs) is generally not suitable for ADCs such as the ADS54RF63 that are operating at high sampling rates with high input frequencies. As you suggest the CDCE72010 or the CDCM7005 with external VCXO has a more suitable jitter performance (~220 fs).  There is a new dual PLL device, the CDCH52005 that is sampling now that achieves good jitter performance and has the flexibility to program to an arbitrary frequency output.

     

    --RJH

     

    From: LeonardEllis [mailto:noreply@e2e.ti.com]
    Sent: Wednesday, October 06, 2010 4:48 PM
    To: int_highspeed_dataconv_forum@e2e.ti.com
    Subject: [INT - High Speed Data Converters Forum] CDCE62005 CLK Driver for ADS5463 [Compiled Designs] vc

     

    Engineer is wanting to use the CDCE62005 as the CLK driver for the ADS5463 (or ADS54RF63) even though I have tried to direct them to the CDCE72010 or CDC7005.  He is wanting to know the specific termination scheme for this interconnect.  The App Notes give choices, from AC-coupled xfrmr to direct connection. 

    Do we have a ref design for this combination of '62005 to ADS5463?  And one for the CDC7005 to the ADS5463?  What advantage/disadvantage of each for this ADC?

    -Leonard

     


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  • 0 in reply to RJ Hopper
    TI__Expert 6040 points

    Leonard,

      I have sent e-mail to CDC group and here is the link, you find the answer from them with the termination setting.

    http://e2e.ti.com/support/clocks/int-clocks/f/50/p/67810/246126.aspx#246126

    Regards,

    Qing

  • 0 in reply to RJ Hopper
    TI__Guru 71526 points

    ADS5463 datasheet specifies a 3V swing for best performance, but the recommendation in SLWA034 - Figure 9 does not achieve that swing.  Are there any numbers available that show the performance degradation if using a 500MHz LVPECL clock?

    One idea is to use the LVPECL clock from the CDCM7005 with a transformer to boost the swing - what effect would this have?

  • 0 in reply to LeonardEllis
    TI__Expert 3865 points

    Leonard,

    on our ADS5463 EVM there is a 4:1 transformer on the clock input to boost the amplitude. I've used the CDCE72010 in conjunction with the ADS54RF63 and have seen very good results with LVCMOS single ended output. A step up transformer definitely can help boosting the clock amplitude (and therefore minimizing the ADC aperture jitter degradation) but the level needs to be watched as not to exceed maximum voltage ratings of the ADC.

    Tommy

  • 0 in reply to Thomas Neu
    TI__Guru 71526 points

    thanks, and do we have any performance characteristic data, compared measurements, with each method?  For a determination of design, engineer is going to want to base their design on tradeoffs between the various methods.

    -Leonard

     

  • 0 in reply to LeonardEllis
    TI__Expert 3865 points

    Leonard,

    I'm working on an appnote on that topic but I need more measurements first before I'm ready for prime time. What I've seen so far is that we have to limit the jitter BW of the clock devices to minimize SNR degradation. However that clock filter eliminates the higher order harmonics which increase the clock signal slew rate. The slew rate has a direct impact on the aperture jitter of the ADC. One way around that limitation is to either use a step up transformer or some type of low noise amplifier.

    I've published two AAJ articles recently on that topic (actually #2 will come this quarter) and #3 will cover the practical implementations (step up transformer, clipping diode, LNA) to improve the performance from CDC devices.

    Tommy

  • 0 in reply to LeonardEllis
    TI__Expert 6040 points

    Leonard,

      The performance is more sensitive to clock jitter than clock amplitude. In the data sheet of 5463 we have SNR, SFDR performance vs clock amplitude shown in figure 59 and 60. These plots are from sine wave and you can see the performance has not much change from the amplitude range of 0.5Vpp to 3.5Vpp differential. I have also tested 5463 EVM recentlly at IF 235Mhz with clock amplitude 0.5Vpp differential the performance is in the typ spec. You can find this data in internal E2E with ADS5463 title.

    Hope this helps,

    Regards,

    -Qing