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ADS127L01: AGND to DGND connection

Eric Thorne
Prodigy 40 points
Part Number: ADS127L01

Hiya,

I've been having conversations with colleagues about the best (lowest noise?) ways to connect AGND to DGND on primarily "analog" devices such as the ADS127L01. 

The datasheet says this:
"The ground plane can be split into an analog plane (AGND) and digital plane (DGND), but this split is not necessary. Place analog signals over the analog plane and digital signals over the digital plane. As a final step in the layout, completely remove the split between the analog and digital grounds. If ground plane separation is necessary, make the connection between AGND and DGND as close to the ADC as possible."

Fair enough, I've read this other places as well, that on an "analog" chip with digital I/O, connect AGND and DGND together as close as possible to the chip on the "analog GND" plane. 

BUT...  The ADS127L01EVM doesn't appear take this advice. See Figure 19 of: www.ti.com/.../sbau261b.pdf, there are two planes, one connected to DGND, and a separate one for AGND under the ADS127L01.  They appear to be shorted together through the board using the plane on the bottom and the GND testpoints which are not near the ADSL127L01. So, why did eval board layout not the datasheet advice? It is not a single physical plane and it is not connected close to the ADC (or am I reading the eval board incorrectly?).

Thanks!

  • 0
    TI__Guru 66346 points

    Hi Eric,

    Thanks for your post.

    I actually did the layout on this EVM, so let me clarify a couple things. First, this design uses an internal plane connected to ground as well as a ground pour on the top and bottom layers (see Figures 19, 20, and 22). All three planes are connected to the same net.

    Now, I did include a partial split in the ground plane, which is mirrored in Figure 19, 20, and 22. Frankly, the reasoning for this is that we were in the midst of solving some other performance issues and we thought it would help separate analog and digital noise coupling. The main culprit turned out to be asynchronous clock signals running to the ADC and to the TIVA uP used in Rev A. We mitigated that issue in Rev B by using a single clock source and a fanout buffer (Y1 and U23).

    Given the placement of components and the expected direction of the return currents to the USB power supply, the split is probably not helping much, if at all. If I had the money to spin the layout again, I'd probably just remove the split altogether after seeing how well the EVM performs now.

    Best Regards,