ADC12DJ3200: About JESD204B RX data arrival time variation

ldx dfdx

Part Number: ADC12DJ3200
Other Parts Discussed in Thread: LMK04828

HI,

I'm now working on a JESD204B core implementation on an XILINX FPGA interfacing an ADC12DJ3200。In the RX end ,I find the data arrival time is varying within a LMFC period.For example ,when set K =4,F=8, sample rate = 4.4GS/S,the LMFC period is 36ns,the data arrival time vary from 410 to 430ns. If I chane K=32,LMFC period is 290ns ,the variation is between 400 to 600ns .It seems I can not get a determinstic latency.

Thanks in advance.

over 7 years ago

0 Jim Brinkhurst1 over 7 years ago

TI__Mastermind 44680 points

Hi
How are you measuring the 'data arrival time'?
Do you mean some lane data is arriving earlier than other lane data when the link is up?
Or are you comparing the latency from signal input to arrival in the fabric when configuring and enabling the system multiple time, ie the latency varies from one system startup to the next system startup?
Is the ADC receiving a SYSREF signal that is frequency and phase locked to the ADC clock?
Is the ADC SYSREF receiver and SYSREF processing enabled?
Have you used one of the available methods to optimize the SYSREF capture CLK timing, either Automatic SYSREF Calibration or SYSREF windowing? (see datasheet section SYSREF Capture for Multi-Device Synchronization and Deterministic Latency).
Which Xilinx FPGA are you using? We do have some example Xilinx JESD204B firmware for the ADC12DJ3200.
Can you share the complete set of register writes you are sending to the ADC?
Best regards,
Jim B

0 ldx dfdx over 7 years ago in reply to Jim Brinkhurst1

Intellectual 400 points

Hi, thanks for your quick reply.
Yes , I am comparing the latency from signal input to arrival in the fabric and it varies from one system startup to the next system startup .
On my board ,I am using LMK04828 to generate ADC CLK(2.2GHz) and SYSREF(2.2GHz/640) .
I've tried automatic sysref calbration,but it seems to have no effect. According to previous test results， the arrival time variation is close to the LMFC period.In other words, reduce LMFC period,the variation would decrease too.
I am using XC7K325T and XC7VX690T.
I‘ve followed the setup sequence in datasheet Page P140 and only changed few register (0x201 =0 0x202 =31 0X204=0X3 0x62 =1).