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ADC12DJ3200EVM: GUI Values for LMX2582 Low Level Always Read 0xFFFF

Drew Boudreau
Prodigy 100 points

Part Number: ADC12DJ3200EVM
Other Parts Discussed in Thread: LMX2582, LMK04828, ADC12DJ3200

When using the EVM GUI the register values for the LMX2582 do not all appear correct.  For instance, when programming the EVM for 1500MSPS and JMODE0 the OUTA/B PD check boxes are always checked.  Viewing Low Level register 46(0x2E) the PD bits are indeed 0 but are not broken out in the Field View section.  If I look at 47(0x2F) the Field View shows the PD bits and indicate they are '1' but in the datasheet those are reserved bits set to '1'.

Also most of the time when a manual Read Register is issued, only for LMX2582, it returns all 1's and this is displayed in the LMX tab.  I am exploring how the LMX gets programmed and these issues are making it difficult. 

I am running windows 10 with a rev A EVM. 

Thank you.          

  • 0
    TI__Mastermind 44680 points
    Hi Drew

    Read-back for the LMX2582 serial interface is not supported with this EVM and GUI.

    You can check the values written to the LMX2582 for the different frequency values by looking at the configuration files which are stored here: C:\Program Files (x86)\Texas Instruments\ADC12DJxx00 GUI\Configuration Files

    The files named LMX2582_xxxxMHz.cfg are the ones of interest.

    Here is an example of the data format:
    LMX2582 - device written in the subsequent commands
    0x40 0x00AF
    0x3F 0x0095
    0x3E 0x0040
    0x3D 0x0001
    0x3C 0x0002
    0x3B 0x0000
    0x3A 0x0000
    0x39 0x0000
    .
    .
    .
    LMK04828 - next device written, commands follow
    0x139 0x00 //set SYSREF_Mux to "Normal"
    0x143 0x11 //set SYNC_MUX to "Pin"
    0x140 0x00 //turn on all the blocks, can these just stay on?
    0x144 0x74 //enable syncing of all clock outputs
    0x143 0x11 //trigger SYNC event using "Pin" mode
    0x143 0x31
    0x143 0x11
    0x144 0xFF //disable syncing of all clock outputs
    0x139 0x3 //set SYSREF_MUX to "Continuous"


    The register address is on the left, and the written value is on the right.

    Certain LMK04828 settings need to be re-written after the LMX2582 frequency is finalized. These writes are included at the end of each LMX configuration file.

    I hope this is helpful.

    Best regards,
    Jim B
  • 0 in reply to Jim Brinkhurst1
    Prodigy 100 points
    Thanks Jim, that clears up a lot. I have looked at LMX2582_1500MHz.cfg but I am having a little trouble deciphering the Fvco value. In the config file there is a line for address 0x26 that states PLL_N is set to 60d for a 6000MHz VCO. PLL_N_PRE is set for 2 (aka 1/2), PLL_NUM is set to 0, and PLL_DEN is 1000d. When I plug those into the following:

    Fvco = Fpd × PLL_N_PRE × (PLL_N + PLL_NUM / PLL_DEN)

    I get 3GHz instead of 6GHz.

    The input path looks to be all 1's so the input to the PFD is the 100MHz oscillator passed through.

    Can you help fill in what I am missing?
    Thanks!
  • 0 in reply to Drew Boudreau
    Prodigy 100 points
    I should add that I believe the Fvco is indeed set to 6 GHz since channel dividers 1 and 2 are set for 2 each, yielding the 1500MHz output clock. I am capturing samples at that frequency so I am clearly missing something in the LMX2582 setup.

    Thanks!
  • 0 in reply to Drew Boudreau
    Prodigy 100 points
    I guess the issue is I expected the PLL_N_PRE value to be 1/2 in the equation but I think it should actually be a 2. Then the equation and examples makes sense.

    Thanks!
  • 0 in reply to Drew Boudreau
    TI__Mastermind 44680 points

    Hi Drew

    I think the error is in my comments in the current file. The note for register 0x26 should say N divider is 30d.

    PLL_N_PRE = 2 (register bit = 0)

    PLL_N value is 30.  

    So Fvco = 100 x 2 x (30 + 0) = 6000 MHz.

    With channel dividers of 2 x 2 = 4, the output is 1500 MHz.

    I did notice that the value being written for register address 0x22 has incorrect default values for the lower 5 bits. Instead of writing 0xC3F0 it should be 0xC3EA.  (lower 5 bits should be 0 1010b instead of 1 0000b )

    I confirmed that writing the proper value instead works fine and doesn't seem to cause any other problems.

    Regards,

    Jim B

  • 0 in reply to Jim Brinkhurst1
    Prodigy 100 points

    Jim,

    I hope it is alright to respond to this thread as it's a similar question and you seem to have authored these configurations.  On the LMK04828 for JMODE0 it appears that PLL1 is enabled by default (everything looks to be configured for the 10MHz external reference).  I am only using the on-board oscillator so I don't believe there is anything to phase detect too and this causes CPOUT1 to go to it's maximum as measured at the oscillator control pin.  I've verified I can force holdover and enable the manual DAC to set the CPOUT voltage.  I just wanted to confirm that this is correct.

    Thank you very much!

    Drew   

  • 0 in reply to Drew Boudreau
    TI__Mastermind 44680 points

    Hi Drew

    That's correct.

    We configure the LMK04828 PLL1 to allow customers to synchronize the ADC12DJ3200 sample clock to an external 10 MHz source. So when 10 MHz is present the 100 MHz VCXO is phase locked to that input. The resulting 100 MHz clock is the reference for the LMX2582.

    If a 10 MHz reference is not present than the VCXO free-runs with the control voltage at max. This hasn't seemed to hurt the phase noise performance on the ADC clock and doesn't cause a significant frequency error. This configuration is convenient since it enables one LMK04828 configuration file to work in 2 different situations.

    If you want to change the settings to drive the PLL1 CPOUT voltage with the manual DAC setting that should be fine too. It will reduce ADC clock frequency error a little. 

    Best regards,

    Jim B