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ADC32RF45: ADC32RF45

Part Number: ADC32RF45

Hi,

I have a question which I assume to be an easy one :).

I am using ADC32RF45 at LFMS=82820 bypass mode at 3GHz sampling frequency. I set the ADC so that it sends 12 bit counter. I am getting counter values in mixed order.  In other words here what I am getting at each lane:

lane 1: c38 c39 c3a c3b c3c 0

lane2:  c47 c48 c49 c4a c4b 0

lane3: c42 c43 c44 c45 c46 0

lane4: c3d c3e c3f c40 c41 0 

What do you think might be causing this confusion?

Thanks in advance.

Erdal

  • E.G,

    Are you enabling the ramp mode? Are the lanes from the ADC swapped when they get to the FPGA per the JESD204B standard? Each lane will have 4 consecutive samples in this mode. It appears you have Lane1 as lane ID0, lane 2 as lane ID4, lane 3 as lane ID3 and lane4 as lane ID2.

    Regards,

    Jim 

  • Hi Jim,

    Yes the ramp mode is enabled. Yes the lanes are swapped, however in my previous message I took this into account and named the lanes accordingly.  What I mentioned as lane 0 in my previous message is indeed lane 4 of the FPGA which corresponds to lane 0 of ADC. I observed something which may help you to spot my problem though. When I reprogram (after powering off and back on again) the FPGA using the .bit  file I happened to see the correct ordering of the lanes from time to time. Do you think this might be something related with the release of the JESD reset, sysref timing or something like that?

    Erdal

  • E.G.,

    We do not see this with our capture board. What is your LMF setting, your K value, and the sample rate and SYSREF frequency? What FPGA are you using? Did you try consulting with the FPGA vendor to see if this is an issue with the IP?

    Regards,

    Jim

  • E.G.,

    Are you still having issues with this? If not, I would like to close out this post.

    Regards,

    Jim

  • Hi,

    The problem still persists. I am planning to contact the FPGA vendor soon but meanwhile I'd appreciate if you have any recommendations. LMFS is set to 82820, K=16, sample rate is 3GHz and sysref freq is set to 2.34375MHz I am using kintex ultrascale and I haven't consulted to FPGA vendor about the JESD204B IP core that I am using. I am planning to do that soon.

    Erdal

  • 3426.ADC32RF45_82820.iniADC32RF45_12bit_82820_Ext_Clk_KCU105.pptxE.G.,

    I got your setup working using a KCU105 and HSDC Pro GUI. You will need to add the attached ini file to the following location on your PC:

    C:\Program Files (86)\Texas Instruments\High Speed Data Converter Pro\KCU105 Details\ADC files.

    I have also included a start up guide for how I did this test.

    Regards,

    Jim