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DAC8531: Relation for power supply and serial interface

Satoshi
Guru 19615 points
Part Number: DAC8531

In the case of FPGA to serial interface: /SYNC, SCLK, and DIN(3.3V), please let me know about two points below.

①Is there power up sequence for VDD/VREF and serial interface?

　Is it no problem for VDD and VREF: 0V and Serial interface: 3.3V?

②If ① is problem, i think that timing margin of VDD/Vref to serial interface are 2.5μs(5VDD), is it correct?

Best regards,

Satoshi

  • 0
    TI__Genius 14220 points
    Hi Satoshi-san,

    Thank you for your query. Please find my answers below:

    1. As per the Abs Max ratings in the datasheet, the digital input voltage should not exceed VDD+0.3V. So, the power-up sequence is: first VDD and then Digital inputs
    2. While the power-up time has been mentioned as 2.5us (VDD=5V) and 5us (VDD=3V), your question refers to the power-on reset to power-up, which is not mentioned in the datasheet, unfortunately. I would recommend a gap of 100us before you start communicating with the device after power up. Please note that the power-on glitch duration is still longer than 100us. If you want to avoid configuring the output during the power-on glitch, you should start programming the DAC much later than 100us. Please see the Power-on Reset plots on pages 7 and 10.

    Hope that answers your question.

    Regards,
    Uttam Sahu
    Applications Engineer, Precision DACs