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DAC38J84: NCO testing

JDY
Prodigy 175 points
Part Number: DAC38J84

hi ,all.

And I have some questions to ask.

I am using a chip DAC38J84 in my design, and l configurate the registers of DAC38J84 by Microblaze in KC705 of Xilinx through a AXI Quad SPI IP core. I remember that there is an answer said by Jim :“Setup the DAC to only use the internal NCO and see if you can get an output. Follow the example attached. This will verify the DAC is getting a valid clock, the power is OK and the SPI is working”. I want to know more detail about how to setup the DAC to only use the internal. Should l configurate the regs by following the steps in section 8.3 of the data sheet? By the way, l don’t use the DAC3xJ8x GUI software to configurate the regs, l use the SDK to config. So do you have the example code to setup the NCO testing?

I would be appreciated for your help.

Best regards,

  • 0
    TI__Guru* 91947 points

    NCO output register settings.csvJDY,

    Attached is an example of an NCO output with the DAC sample rate at 100MHz. You will need to update registers 0x12-0x19 to reflect the sample rate you are using for the DAC clock and the desired NCO frequency.

    Regards,

    Jim

  • 0 in reply to jim s
    Prodigy 175 points
    hi Jim，

    l have configurated my DAC38J38's regs as the "NCO output register setings.csv" you gave me. But there is nothing output. Are there all the regs listed in the file"NCO output register setings.csv" l need to config? Or there is some regs else l also need to config?

    Regards,

    JDY
  • 0 in reply to jim s
    Prodigy 175 points
    Hi Jim,

    By the way, the pin SYNCB of DAC38J84 is active low or active high? What's more, My colleague used to push the 3.3V power to 6V and keep about 4 seconds carelessly . So is there any possible , l think, that the chip has been ruined?

    PS: Through the pin ALARM, l can confirm that the PLL and clock is OK and the JESD has been setup, but there is no data output from the chip.

    Regards,

    JDY
  • 0 in reply to jim s
    Prodigy 175 points

    Attached is my register setting. DAC sample rate is 250MSPS, LMFS=8421,no interpolation. The serdes line rate is 2.5Gbps. And the external DAC CLK is 250MHZ.dacreg.docx

  • 0 in reply to JDY
    TI__Guru* 91947 points

    JDY,

    Did you issue a hard reset after power and the clock were present? Is TXENABLE high? If not, there will be no output. There is a chance you may have damaged the part when operating at 6V.

    Regards,

    Jim

  • 0 in reply to jim s
    Prodigy 175 points

    hi Jim,

    l have reset my chip by config the reg 0x02 bit0. Must l hardware reset it? And TXENABLE is high.

    Regards,

    JDY

  • 0 in reply to JDY
    TI__Guru* 91947 points

    JDY,

    Yes, you must do a hardware reset.

    Jim

  • 0 in reply to jim s
    Prodigy 175 points

    Jim,

    l have done the reset, and the TXENABLE is high . But it's still nothing output. l am very confused. Here is my NCO testing config:

    0x2F0001,
    0x302000,
    0x022050,

    0x1BC100,

    0x1A0020,
    0x317808,
    0x320360,
    0x33AF70,
    0x3B0000,
    0x3C9050,
    0x3D00B6,
    0x3E0148,

    0x143333,
    0x153333,
    0x163333,
    0x173333,
    0x183333,
    0x193333,
    0x120000,
    0x130000,
    0x1F1140,
    0x1F1142,
    0x1F1140,
    0x03F301

    Can you help verify this config? DAC CLK=250MHz


    YJD