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ADS5444: clock input compatibility with lvds and lvpecl

Part Number: ADS5444

Is it possible to supply clock inputs of this adc with lvds or lvpecl logic?

Thanks.

  • Hi Aseok,

    LVPECL with AC coupling should be able clock the ADC.

    Regards,
    Neeraj

  • I decided to use AD9517-4 LVPECL outputs for clocking the ADC, Is this circuit scheme suitable?

  • Hi Neeraj 

    As i decide to capture converter data with xilinx spartan 6 family for initial tests, i wonder is it possible to clock the converter with lvds clock outputs of sp6 family?

    I searched and found some contradictory information regarding the possibility of this connection and it's configuration type (termination resistors, etc.).

    In AN1318 of STMicroelectronics titling "INTERFACING BETWEEN LVDS AND HIGH SPEED DIFFERENTIAL LOGIC FAMILIES", it is mentioned that:



    these statements seem to be in contradiction. 
     

  • Hi Aseok,

    I can't comment on AD9517 device.

    Regards,
    Neeraj Gill
  • But my last question is about clocking the ADC with fpga, without the use of AD9517 device.
  • Hi Aseok,

    1. The nominal clock amplitude required for ADS5444 is 3Vpp differential. Lower amplitude clock may degrade the ADC performance.
    2. I am not sure how clean the clock from FPGA will be. The quality of you clock signal will also affect ADC performance. I would recommend post on TI's clock and timing E2E forum and ask for recommendation on which is suitable device for your application.

    Regards,
    Neeraj Gill