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ADS7946: Low SCLK rate

Mark Guastaferro
Genius 11645 points
Part Number: ADS7946

Are there any concerns with using the ADS7946 with a SCLK clock rate of 2-4 MHz?  The processor that is controlling this ADC cannot run the SPI bus much faster than this, and a sample rate of 100k-200ksps is good enough for the application. 

The data sheet provides a max clock rate, but not a minimum. There is information about running at lower sample rates, but this still assumes a 40 MHz SCLK.  

  • 0
    TI__Guru 55466 points

    Hi Mark,

    The ADS7946 ADC operate without issues at a SCLK frequency of 2-4MHz; as long as the timing parameters of Table 1 are met.

    A lower frequency SCLK can be used for sampling rates less than 2 MSPS. However, it is better to use a 40 MHz SCLK and slow down the device speed by choosing a lower frequency for CS, which allows longer acquisition time.

    There is no explicit low limit for SCLK frequency.  If an extremely low SCLK frequency is used, the Sample-and-Hold leakage could become an error source due to leakage currents. However, there is no issue operating at 2-4MHz.  Since the frame consists of about ~16 SCLKs, the maximum sampling rate achievable is~117kHz

    Thank you and Best Regards,

    Luis

  • 0 in reply to Luis Chioye
    TI__Genius 11645 points
    Hi Luis,
    Thanks for the quick response and details.

    One question - how did you calculate the max sampling rate to be ~117 KHz. 16 clocks at 4 MHz plus 80ns acquisition time results in a rate above 200 KHz. Am I miscalculating something?
  • 0 in reply to Mark Guastaferro
    TI__Guru 55466 points
    HI Mark,

    The post above mentions you may use 2-4MHz SCLK frequency; therefore, using the worst case 2MHz SCLK frequency, and assuming you are using ~17xSCLKs per frame, that is 16 SCLKs to read data and 1 SCLK to perform the CS toggle, this yields approximately ~117kSPS.

    Yes, you are correct, if the controller you are using allows you to use 16 SCLKs + accurately use a min acquisition time of 80ns to toggle CS, assuming SCLK frequency 4MHz, this would yield ~245kSPS; and at SCLK frequency of 2MHz this yields 123.7kSPS.

    Many Thanks,
    Luis
  • 0 in reply to Luis Chioye
    TI__Genius 11645 points

    Hi Luis,

    OK this makes sense.  I forgot that the CS pulse width will probably be the same as the SCLK timing.