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ADS1281: Master clock input sequence

NAOKI AOYAMA
Guru 11215 points

Part Number: ADS1281

Hello,

Our customer use the ADS1281, have a question about clock input timing.

Refer to the Figure 42, the clock signal is input before DVDD.

But the absolute maximum ratings of the digital input is less than DVDD+0.3V.

Is the clock input timing of the figure 42 correct?

Should the customer input the clock after power on?

Best Regards,

Naoki Aoyama

  • 0
    TI__Mastermind 44760 points

    Hi Naoki-san,

    That is a good question!

    The customer is correct about the input voltage requirements...there should not be any voltages applied to the device that exceed DVDD unless they are current limited. Therefore, I would recommend powering the device and then enabling the external clock signal.

    Please note that after enabling the external clock that the 2^16 clock period delay is still required and is now referenced to the point in time when the external clock is enabled.

    Figure 42 was trying to show that the AVDD and DVDD supplies must reach a certain threshold AND that 2^16 clock periods must complete before you begin communication with the device. However, it would have been better drawn if the CLK signal began after the supplies were enabled.

    Please let me know if I was able to answer your customer's question, or if there are any additional questions I can help with!

     

    Best regards,
    Chris

  • 0 in reply to Christopher Hall
    Guru 11215 points
    Hello Chris,

    Thank you for your reply.
    I understood the power on sequence.
    I will feedback the customer this information.

    Thanks,
    Naoki Aoyama