ADS54J42：ads 54j42

 in my fpga ,the ad data is 0x02000100,0x01000100,0x00800080 ,  if byte reverse, 0x00020001,0x00010001,0x80008000, this result is the same with  section 5.1.6.3 of the JESD204B specification. am i right? if i am right, which reg should set?

User,

Do you issue a hard reset to the ADC after power and clocks are provided? Do you follow the power up sequence per the data sheet? Can you send your ADS54J42 register settings?

Regards,

Jim

1,table 52  testmode set 1 , then what is result adc should output ?

 in my fpga ,the output is ox02000100,0x01000100,0x00800080 ....and so on , i don't know  the result is right or wrong ?  

tthe testmode result should be same as per section 5.1.6.3 of the JESD204B specification. but i do not understand i datasheet .

2,in table 55 layer test mode set 1, table 52  testmode set 1 or 0? set 0,  i my fpga ,the sync does not pull high . using layer testmode how set table 55 and table 52

lmfs = 1241 ,my ads54j42 register setting as below,

//reset device
ad_spi_write_dw(0x0000,0x81);/// Internal software reset, clears back to 0
ad_spi_write_dw(0x4001,0x00);///Clear any unwanted content from the unused pages of the JESD bank.
ad_spi_write_dw(0x4002,0x00);///Clear any unwanted content from the unused pages of the JESD bank.
ad_spi_write_dw(0x4003,0x00);/// sel main digital page
ad_spi_write_dw(0x4004,0x68);/// sel main digital page
ad_spi_write_dw(0x60f7,0x01);///reset digital block
ad_spi_write_dw(0x6000,0x01);///Pulse the PULSE RESET bit (so that register writes to the main digital page go into effect).
ad_spi_write_dw(0x6000,0x00);///Pulse the PULSE RESET bit (so that register writes to the main digital page go into effect).
//perfermence modes
ad_spi_write_dw(0x0011,0x80);///Select the master page of the analog bank.
ad_spi_write_dw(0x0059,0x20);///Set the ALWAYS WRITE 1 bit.
ad_spi_write_dw(0x0039,0x00);///ad sample fre <400 ,set 0
ad_spi_write_dw(0x003a,0x00);///ad sample fre <400 ,set 0
ad_spi_write_dw(0x0056,0x00);///ad sample fre <400 ,set 0
//programe desired register
ad_spi_write_dw(0x4003,0x00);///sel jesd digital page
ad_spi_write_dw(0x4004,0x69);///sel jesd digital page
ad_spi_write_dw(0x6000,0x80);///bit[7]:ctrl K,bit[4]:test mode en bit[0]: ila-----------------------------------------
//analog bank jesd link config
ad_spi_write_dw(0x6016,0x90);///bit[7]: must write 1,bit[4]:Lane sharing is enabled, both channels share one lane(LMFS = 1241)
ad_spi_write_dw(0x6031,0x0A);///DA bus order
ad_spi_write_dw(0x6032,0x0A);///DB bus order
ad_spi_write_dw(0x6001,0x22);///jesd register 01
ad_spi_write_dw(0x4003,0x00);///sel jesd anolog page
ad_spi_write_dw(0x4004,0x6a);///sel jesd anolog page
ad_spi_write_dw(0x6016,0x02);///pll mode 40X mode
ad_spi_write_dw(0x6017,0x40);///The PLL RESET bit is pulsed
ad_spi_write_dw(0x6017,0x00);///The PLL RESET bit is pulsed ,0 --1 -- 0
ad_spi_write_dw(0x4003,0x00);/// sel main digital page
ad_spi_write_dw(0x4004,0x68);/// sel main digital page
ad_spi_write_dw(0x604d,0x08);///decimation enable
ad_spi_write_dw(0x6041,0x10);///DECFIL EN = 1 ,The DECFIL MODE[3:0] ,41 register bit5 = 0 and bit[2:0] = 000 ,bit 3 must 0
ad_spi_write_dw(0x6052,0x80);///ddc mode only must write bit7 1
ad_spi_write_dw(0x6072,0x08);///ddc mode only must write bit3 1
ad_spi_write_dw(0x6000,0x01);///Pulse the PULSE RESET register bit. All settings programmed in the main digital page take effect only after this bit is pulsed
ad_spi_write_dw(0x6000,0x00);///Pulse the PULSE RESET register bit. All settings programmed in the main digital page take effect only after this bit is pulsed
ad_spi_write_dw(0x4003,0x00);///sel jesd digital page
ad_spi_write_dw(0x4004,0x69);///sel jesd digital page
ad_spi_write_dw(0x6006,0x08);///set K

but your engieer sent me config file that mode = 1241 as below,

//reset device
ad_spi_write_dw(0x0000,0x81);/// Internal software reset, clears back to 0
ad_spi_write_dw(0x0011,0x80);///Select the master page of the analog bank.
ad_spi_write_dw(0x0059,0x20);///Set the ALWAYS WRITE 1 bit.

ad_spi_write_dw(0x4001,0x00);///Clear any unwanted content from the unused pages of the JESD bank.
ad_spi_write_dw(0x4002,0x00);///Clear any unwanted content from the unused pages of the JESD bank.
ad_spi_write_dw(0x4003,0x00);/// sel main digital page
ad_spi_write_dw(0x4004,0x68);/// sel main digital page
ad_spi_write_dw(0x60f7,0x01);///reset digital block

ad_spi_write_dw(0x6041,0x10);

ad_spi_write_dw(0x6072,0x08);

ad_spi_write_dw(0x6052,0x80);

ad_spi_write_dw(0x604D,0x08);

ad_spi_write_dw(0x6000,0x01);

ad_spi_write_dw(0x6000,0x00);

ad_spi_write_dw(0x4003,0x00);///seljesd digital page
ad_spi_write_dw(0x4004,0x69);///seljesd digital page
ad_spi_write_dw(0x6000,0x80);///bit[7]:ctrl K,bit[4]:test mode en bit[0]: ila-

ad_spi_write_dw(0x6006,0x0F);/// Set K = 16

ad_spi_write_dw(0x6001,0x22);///jesd filter and mode

ad_spi_write_dw(0x6016,0x10);///

ad_spi_write_dw(0x6000,0x31);///

ad_spi_write_dw(0x6000,0x32);///

i don't understand why K set 16?

last two line is

ad_spi_write_dw(0x6000,0x31);///

ad_spi_write_dw(0x6000,0x32);///

i don't understand ,pls explain?

my ad freqency = 300M, sysref =  ad freqency /4 /(k+1) / 8 = 1.04M .

in 204b ip  transmit sysref = 300M , core clk = 75M that generate by my fpga pll,not same source with ad freqency.

User,

I am looking into the long transport issue you are seeing. Can you tell me the mode (LMFS) you are planning on using, K value, and decimation rate? I will set up a system to operate with your settings and send you the required configuration file for the ADC.

Regards,

Jim

lmfs=1241,k=8,ad sample rate = 300m, 1/4 decimate,decimate rate=75m,why you don't see my reply,i write very clear!

User,

In table 52, with testmode set to 1 (bit 4), the ADC output will be the long transport test pattern. 

In table 55, if layer test mode is selected, you must have table 52 testmode set 0. The link will no longer be valid, that is why the FPGA will not assert SYNC. The ADC will just send continuous test data based on what is selected. 

Regards,

Jim

what's  the long transport test pattern should out put?in my fpga, use lmfs=1241,the data stream is 0x02000100,0x01000100,0x00800080 .....and so on. idon't know the result is right or wrong?

what's  the long transport test pattern should out put?in my fpga, use lmfs=1241,the data stream is 0x02000100,0x01000100,0x00800080 .....and so on. idon't know the result is right or wrong?

i know byte swap, but i don't know why?

i am confuse why my data swap?

i don't know why my data swap? can you figure out it?

user,

Can you send a captured plot of a an output with a 1MHz tone input? After this, do another capture with bit 3 of add 0x00 of page 0x6900 set to "1" to swap the ADC output to MSB to LSB. What FPGA are you using to capture the data with? You may have to consult with the FPGA vendor to find out if you may have a setting wrong in the JESD204B IP.    

Regards,

Jim