ADC12D1600RF: clock jitter requirements

assaf matia

Part Number: ADC12D1600RF

HI,

in the datasheet (6.1.2.5) regarding input clock jitter (Tjmax), there is a formula using 2^(N-1) where N is the ADC resolutions in bits.

my question is, does N in this device is 12 or should I look at the ENOB, where its mentioned that the effective number of bits is actually ~9. (looking at the datasheet tables and graphs for my input frequency and mode).

since my frequency is around 1300MHz , I get Tj=~15fSEC if N=12 and Tj=~120fSEC if N=9.

which is the correct calculation and why?

thanks

over 7 years ago

0 Jim Brinkhurst1 over 7 years ago

TI__Mastermind 44680 points

Hi Assaf

For that calculation you should be using the target ENOB for your application.

You may also be interested in this application note (AN-1558) which discusses the allowable clock jitter given target SNR, input frequency and ADC intrinsic aperture jitter specifications.

Here is the direct link to the application note: http://www.ti.com/lit/an/snaa036b/snaa036b.pdf

Best regards,

Jim B

0 assaf matia over 7 years ago in reply to Jim Brinkhurst1

Prodigy 240 points

thanks!!

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ADC12D1600RF: clock jitter requirements