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ADC10065: input impedance

domenyko
Genius 9655 points

Part Number: ADC10065
Other Parts Discussed in Thread: THS4521

Dear all,

one of my AA is noticing high offset (after the conversion) and he thinks is due to some imbalance at the input of the ADC.

The ADC10065 is driven by a THS4521 op amp. The op amp and the ADC seats on 2 different boards. The offset is noticed also when a simple DC signal is connected to the ADC.

Up to now (this is an old project) there wasn't any offset issue and he thinks that the lot of ADC he has received has a different input impedance. He would add a matching resistor network to re-balance the impedance.

In the Datasheet there isn't any info onthe resisitve impedance of the input stage of the ADC. Are there any data available ? (typical and variations).

regards,

Domenico

  • 0
    TI__Mastermind 44680 points
    Hi domenyko
    Is it possible to share the schematic for the ADC10065 and THS4521 and related circuitry?
    How much offset is being seen? Given a specific DC input, what is the expected output code and what actual output code is being seen?
    Thanks,
    Jim B
  • 0 in reply to Jim Brinkhurst1
    TI__Mastermind 44680 points

    Hi Domenico

    The ADC10065 input pins are not terminated on chip and are un-buffered. The sampling capacitance is present at the inputs, and the capacitance changes slightly as the CLK toggles and the sample/hold switch opens and closes.

    As the datasheet notes in the SIGNAL INPUTS section:

    "The internal switching action at the analog inputs causes energy to be output from the input pins. As the driving source tries to compensate for this, it adds noise to the signal. To prevent this, use 18Ω series resistors at each of the signal input pins with a 25 pF capacitor across the inputs, as shown in Figure 42. These components should be placed close to the ADC because the input pins of the ADC is the most sensitive part of the system and this is the last opportunity to filter the input. The two 18Ω resistors and the 25 pF capacitor form a low-pass filter with a -3 dB frequency of 177 MHz."

    If the driving circuitry doesn't incorporate these R/C features that may be the cause of the offset issue.

    I hope this is helpful.

    Best regards,

    Jim B

  • 0 in reply to Jim Brinkhurst1
    TI__Genius 9655 points

    Hi Jim,

    thanks for the hints. Between the OP AMP and the ADC there is a LC filter plus a capacitance very close to the the input pins of the ADC.

    The designers are going to set up a bench to debug the isse. They wil share test results, schematic and layout.

    regards,

    Domenico

  • 0 in reply to domenyko
    TI__Genius 9655 points
    Hi Jim,
    some other details on the bypass of the ADC:

    pin6 Vref and pin7 Vreft: are bypassed wiht 1uF cap at each pin.

    pin4 Vcom is driven wiht 1.25V and there is 1uF bypass cap;

    pin8 Vrefb, is floating without any bypass cap (error in the schematic)

    Which could be the effect of the missed bypass cap at Vrefb pin ?

    regards,
    Domenico
  • 0 in reply to domenyko
    TI__Mastermind 44680 points

    Hi Domenico

    Per the datasheet, Vcom, Vreft and Vrefb should be decoupled to analog ground with 0.1uF capacitance. Having 1uF on Vreft and no capacitance on Vrefb could cause issues with conversion accuracy and performance of the ADC. I don't know enough about the specific impact but recommend the design be corrected so the same 0.1uF capacitors are used on both reference pins, and on Vcom.

    Driving Vcom is not an allowed usage. Vcom can be used as an output to set the common mode voltage of the external driving circuitry. Figure 42 in the datasheet shows how this can be done for a transformer coupled input. If an external amplifier is used the Vcom signal should be buffered to minimize the current loading on the Vcom pin.

    It is allowed to drive the Vref pin with an external 1.2V reference voltage if greater accuracy is desired.

    I hope this is helpful.

    Best regards,

    Jim B