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ADC08D1520: DCLK question with respect to I & Q outputs

Mark Pearson
Genius 12705 points
Part Number: ADC08D1520

My customer has sent me the following:

We are running the ADC08D1520 in 1:2 Demux Non-DES Mode, using a DDR output data clock.

 

So, for each edge of the output data clock, there is an I and an Id, and a Q, and a Qd.

 

With the I and Q channels functioning independently of each other, can I use DCLK for both I and Q?  I think I don’t need to use DCLK for I and DCLK2 for Q?

 

I think that is what this means from page 50 of the datasheet.

There is one LVDS output clock pair (DCLK+/-) available for use to latch the LVDS outputs on all buses. There is

also a second LVDS output clock pair (DCLK2+/-) which is optionally available for the same purpose.

I’ve done some experimenting, and when cross correlating the I and Q channels, it appears that I do need to clock in the entire bus using the one primary DCLK for one of the measurements we are trying to perform.

Using the auxiliary clock for the Q channel causes a spread in the measurement result.

Thoughts on this matter?

  • 0
    TI__Mastermind 44680 points

    Hi Mark

    The customer is correct. They can use just the default DCLK output as the data capture clock for both I and Q channel data. The second DCLK output was provided to ease design in some customer systems where separate FPGA or ASIC banks were capturing the I and Q data. In those systems one DCLK would accompany the data sent to each bank.

    They should be able to use both clocks if desired or needed, the skew between DCLK and DCLK2 outputs is very low. I'm not sure why they saw "spread" in results when using two DCLKs. To analyze that further I would recommend capturing data using the Test Pattern Output in both single and dual DCLK configurations to understand what is happening with capture data integrity and alignment.

    Best regards,

    Jim B