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ADS1148: Regulation time of START pin toggle(Low->High)

Hirotaka Matsumoto
Guru 27585 points
Part Number: ADS1148

Hi all

Would you mind if we ask ADS1148?

We would like to know whether there is regulation time of START pin toggle(Low->High) regardless of tCONV.
For example, if there is regulation time of START pin toggle(Low->High), we would like to know the time(term) between 2. and 3.  

1. WREG command settting : START pin keeps High 
2. After WREG command settting : START pin Low
3. Starting of convesion and RDATA(getting conversion data) at regular intervals : START pin toggles(pulse)

If the START=Low term is short, we worry whether ADC1148 can recognize the pulse of START correctly or not. 
(Of course, in order to get conversion data exactly, it requires tCONV.)

Kind regards,

Hirotaka Matsumoto

  • 0
    TI__Guru* 97545 points
    Hirotaka-san,


    If you are asking what is the minimum low time for the START pin, it is 3 tCLK. This is the same as the minimum START pulse of tSTART show in the timing requirements on page 11. If the device is using a clock of 4.096MHz, this is about 7.4us. If the internal oscillator is being used, then the oscillator has a 5% variance, and you should use something closer to 8us. This is the time it takes for the START pin to be latched into the master clock domain in the digital section of the device.

    Note that between 2) Start pin low after WREG and 3) RDATA and START pin toggles to start a new conversion, you must wait for the conversion to complete as indicated by /DRDY. If the START pin is toggled before the conversion completes, the conversion is interrupted without getting new data and a new conversion starts.

    I think this is what you were asking in your last post. If I've misunderstood your question feel free to post back.


    Joseph Wu