ADS131A04: Question about setting for VNCP, /DRDY timing, and input connection

Satoshi

Guru 19645 points

Part Number: ADS131A04
Other Parts Discussed in Thread: OPA1678,

Please let me know about three points below for ADS131A04 setting.

①Negative charge pump output(NVCP)

　If VNCP unused, is VNCP really connect AVSS, OK?

　EVM user's manual P16 is described that JP8 should to connect after setup.

　Is this condition only the case of use NVCP?

② Timing for /DRDY and clock (CLKIN or SCLK)

　Please let me know about recommended timing for /DRDY and clock.

　Customer is worry about metastable,

　・This case is /DRDY made by CLKIN rise, but the margin of Tdelay is small.

　・This case is /DRDY made by CLKIN fall, but I think possibility of metastable.

③Input connection

　If ADS131A04 input side(AINx) is connecting OPA1678, is RC filter necessary to connect between OPA1678 output and ADS131A04 input?

　Or is direct connection no problem?

Best regards,

Satoshi

over 7 years ago

0 Ryan Andrews over 7 years ago

TI__Guru 66346 points

Hello Satoshi-san,

Thank you for your post.

Satoshi said:
①Negative charge pump output(NVCP)

Please refer to the Pin Functions table on pages 5 - 6 of the ADS131A04 datasheet. VNCP must be connected directly to AVSS if the negative charge pump is unused. On the ADS131A04EVM, this can be done by installing JP8.

Satoshi said:
② Timing for /DRDY and clock (CLKIN or SCLK)

Which mode is the customer using?

Satoshi said:
③Input connection

The RC filter at the ADS131A04 inputs serve two purposes. First, the differential capacitor provides charge to the internal sampling capacitors. This helps the input voltage settle more quickly between modulator samples. Second, the series resistance needed for amplifier stability also forms a single-pole, low-pass filter for antialiasing.

Best Regards,

0 Satoshi over 7 years ago in reply to Ryan Andrews

Guru 19645 points

Ryan-san

Thank you for reply,
I answer your question ② below;

Customer hope "the case of /DRDY made by CLKIN fall".
But if there the other good idea, customer will consider this idea.

Best regards,
Satoshi

0 Ryan Andrews over 7 years ago in reply to Satoshi

TI__Guru 66346 points

Hello Satoshi-san

I was referring to the interface mode. Is the customer using Asynchronous Interrupt Mode, Frame-Sync Master Mode, or Frame-Sync Slave Mode?

Best Regards,

0 Satoshi over 7 years ago in reply to Ryan Andrews

Guru 19645 points

Ryan-san

Sorry for my reply delay,

Customer is using Frame-Sync Slave Mode.

Additional question for ③, which is recommended connection below? (R value are 1~2kΩ)

I think that number ④ is better, is it correct?

Best regards,

Satoshi

0 Ryan Andrews over 7 years ago in reply to Satoshi

TI__Guru 66346 points

Hello Satoshi-san,

Thank you for the details.

In "Synchronous Slave Mode" (sorry for using the wrong name before), the internal clock source (ICLK) can be generated from either the external signal connected to the XTAL1/2 or CLKIN pins (CLKSRC = 0) or from the SCLK input (CLKSRC = 1). Which setting is your customer using?

The timing specifications for both CLKSRC settings are described as tSU(sync) and tH(sync) = 10 ns (minimum) in Figure 4 and Figure 5.

In Figure 4 (CLKSRC = 0), it is ok to align /DRDY falling edge with CLKIN rising edge. You must keep the CLKIN falling edge at least 10ns after the /DRDY falling edge.

In Figure 5 (CLKSRC = 1), it is ok to align /DRDY falling edge with SCLK falling edge. You must keep the SCLK rising edge at least 10ns after the /DRDY falling edge.

Either circuit (3) or (4) will work fine. I believe (3) will provide better common-mode rejection.

Best Regards,

Data converters

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ADS131A04: Question about setting for VNCP, /DRDY timing, and input connection