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I am guessing the power will be routed to internal power planes with GND layers either above them or below them or both. You can then route the JESD204B serdes lanes on the top or bottom layers maybe along the top or bottom edge of the board to stay clear of the power devices. For instance, if you have the regulators on the top of the board, I would try to route the serdes on the bottom of the board or layers near the bottom. The trace length is not critical for the serdes lines and the pair to pair routing can have a lot of skew due to the elastic buffer feature of this standard. If using internal layers for these, make sure there is a continuous GND plane above and below the signal traces with no splits. See the attached document for more guidelines for routing these signals. You can download the board design files for all of our high speed data converter JESD204B EVM's, including the ADC32RF45EVM for an example. These are located under the product folders on the TI website.
