ADS1148: tSCCS regulation and reset of SPI transmit using CS=High

Hirotaka Matsumoto

Part Number: ADS1148

Hi all

Would you mind if we ask ADS1148?

<Question1>
There is the tSCCS regulation on the datasheet P12.
In this case, until CS turns low to high(end of SPI transmission), SCLK is low.
If CS turns low to high(end of SPI transmission) with SCLK keeping high, is there anything problem?
Our customer asked us it.
However, we assume that ADS1148 can't judge whether SPI transmission terminated or not.

<Question2>
We would lile to confirm SPI Reset.
When the CS pin can be pulled high, SPI transmission returns to initial condtion.
Is our recognition correct?

Kind regards,

Hirotaka Matsumoto

over 7 years ago

0 Joseph Wu over 7 years ago

TI__Guru* 97775 points

Hirotaka-san,

1. I'm not exactly sure what you're describing by keeping SCLK high. The last bit is clocked into the device as SCLK goes from high to low. After that, it is certainly possible to take SCLK high, but it doesn't change tSCCS. tSCCS is the required time from the last SCLK going low to the rising edge of /CS.

I believe that the tSCCS specification is for timing in a WREG command. If the tSCCS is too short (less than 7 tCLKs), the last byte to be written to the device may not get written into the configuration register.

2. Yes, I believe the SPI is held in reset when the /CS is pulled high, therefore after the /CS returns low, the SPI comes out of reset and the SPI communication starts over at the beginning. Note that there is a minimum for /CS. This is given as tCSPW in the Timing Requirements as 5 tCLKs.

Joseph Wu

0 Hirotaka Matsumoto over 7 years ago in reply to Joseph Wu

Guru 27585 points

Joseph san

Thank you so much for your support always!
OK, we got it.

Kind regards,

Hirotaka Matsumoto

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ADS1148: tSCCS regulation and reset of SPI transmit using CS=High