• State Resolved
  • Locked Locked
  • Replies 1 reply
  • Subscribers 46 subscribers
  • Views 503 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

ADC08D1520: VHDL question and Test Pattern Question

Mark Pearson
Genius 12705 points
Part Number: ADC08D1520

I have an evaluation board for the ADC08D1520.  Is there VHDL code for the Virtex-4 FPGA that is on that board?  The box only has the board in it now, so I don’t know if there was source code for the FPGA included.  I want to see how the inputs were set up in that FPGA code.

Test Patter related question:  I am adjusting the input delay for clocking the data into the FPGA.  I found a point where the measurement dropped off to nearly nothing.

 

I then set the ADC’s to output the test pattern, because I wanted to see how the test pattern looked in this state.  The test pattern looked perfect!

 

I was trying to use the test pattern to find where to center the data to clock delay, but the test pattern looked good throughout the range.

 

Is there something different going on when the ADC’s send out the test pattern vs. sending out regular data?

Thanks!

  • 0
    TI__Mastermind 44680 points
    Hi Mark
    The FPGA source code for the ADC08D1520RB is included in the ADC0xD1520RB Design Package available for download in the Design files section of the web page.
    Regarding the test pattern question. The only difference between ADC data mode and the Test Pattern Mode should be the information in the ADC data. The timing relationship between the output data and DCLKs should not change. If the data capture delay is adjusted to the point where capture is happening during the 0->1 or 1->0 transitions in the data bits I would expect to see bad data values for both normal data mode and test pattern mode. The behavior may be slightly different due to the predictable bit sequence in TPM versus unpredictable with real data, but in general bad data values should be seen with either data type.
    Best regards,
    Jim B