ADC12DJ3200: Vih max level of ADC

Ayesha fakruddin

Intellectual 360 points

Part Number: ADC12DJ3200

Please specify Vih max level of ADC12DJ3200

over 6 years ago

0 Jim Brinkhurst1 over 6 years ago

TI__Mastermind 44480 points

Hi Ayesha

Which device pin specifically are you asking about?

The Vih and Vil levels for the CMOS inputs are listed in section 6.3 Recommended Operating Conditions.

Best regards,

Jim B

0 Ayesha fakruddin over 6 years ago in reply to Jim Brinkhurst1

Intellectual 360 points

Hi Jim,

In section 6.3 Vih min is specified but we need the maximum limit for Vih. Can all the ADC control pins be directly connected to 1.8V CMOS bank of the FPGA or a buffer/level translator is required?

Regards,

Ayesha

0 Jim Brinkhurst1 over 6 years ago in reply to Ayesha fakruddin

TI__Mastermind 44480 points

Hi Ayesha

The Vih min is listed as 0.7V for the LVCMOS inputs. Any voltage at or above 0.7V will be recognized as a logic high.

The absolute maximum voltage that can be applied there is listed in table 6.1 as VA19+0.5V.

I recommend using a 1.8V bank from the FPGA for all of the ADC LVCMOS inputs.

Best regards,

Jim B

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ADC12DJ3200: Vih max level of ADC