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DAC38J82: NCO configuration for dac38J82

Part Number: DAC38J82
Other Parts Discussed in Thread: DAC38J84

Hi,

I have dac38J82 evm.

For NCO configuration, I am using following register settings.

1. config 0 is 0x218. 

2. config 2 is 0x2052 (mixer is enabled and nco is enabled)

3. config 31(0x1F) is 0x9980.

4.register  0x14 to 0x00

5.register  0x15 to 0x00

6. register  0x16 to 0x4000

This is a simple example of Fs/4, I am using now. I would like to change it later.

7. For sif sync, I am set bit 1 of 0x1F. wait 10 msec and then set it to zero.

Can you please check my configuration?

If I want to change settings again,

I am just changing registers 0x14 to 0x16 and then toggling sif sync bit.

Please let me know if I am missing any step. 

Thanks,

Mallesh

  • Hi Mallesh
    We have received your question.
    Someone will respond in more detail soon.
    Best regards,
    Jim B
  • Hi Mallesh,

    Here are instruction for using the NCO/Mixer.

    DAC38J84 Programming Complex Mixers

    The DAC38J84 supports both coarse mixing and fine mixing options. Fine mixing provides flexible frequency placement, and coarse mixing option is a subset of fine mixing option to allow pre-calculated arithmetic to save additional power consumption. Enable one of two mixing options to fulfill the frequency placement requirements.

    1. Enable Complex Mixer: set config2, bit6 to 2b’1.

    2. Enable either coarse mixer or fine mixer:

    (a) For coarse mixer setting, set config13, bit15:12 to the desired coarse mixing options. The DAC38J84 has

    coarse mixer options of –fs/4, fs/2, fs/4, fs/8, 3fs/8, 5fs/8, and 7fs/8. Set config2, bit 4 to 2b’0 to disable fine mixing.

    (b) For fine mixer setting, set config2, bit 4 to 2b’1. This enables the full NCO block for fine mixing. Set config13, bit15:12 to 2b’0000 to disable all coarse mixing  options.

    (c) Note: TI recommends enabling only one of the two options.

    3. Fine mixer option requires additional configurations as discussed below:

    (a) Program the NCO frequency and phase offset registers in DSP path channel AB and channel CD. The corresponding registers are config18 to config25.

    (b) The fine mixers and NCO are counter circuits and require initialization sequence for the arithmetic and correct output. These circuits can be initialized by one or more initialization signals such as auto-sync signal from register programming, SYSREF input, sync-out signal from JESD block, and SIF register sync. Register config31 provides the initialization setting.

    4. Example Fine Mixer and NCO Programming and Initialization setting using SIF register sif_sync:

    (a) Requirements:

    (a) FNCO = 122.88MHz

    (b) FNCO_CLK = FDAC = 2457.6MHz

    (b) Calculations:

    (a) Frequency = FNCO x 2^48 / 2457.6MHz = 14073748835533 = 0x CCCCCCCCCCD = 2b’0000-1100-

    1100-1100-1100-1100-1100-1100-1100-1100-1100-1101

    (b) One method to program negative frequency is to first calculate the binary bits of positive frequency.

    The next step is to invert all the binary bits of the positive number and add one to the end to form the

    negative number. For instance, -122.88MHz = 0xF33333333333 = 2b’ 1111-0011-0011-0011-0011-

    0011-0011-0011-0011-0011-0011-0011

    (c) Program the calculated frequency values into config20 to config22 for channel AB path, and config23 to

    config25 for channel CD path. Program the phase offset values for channel AB path and channel CD

    path in config18 and config19, respectively.

    (d) Program config31 as 0x8880 such that the fine mixers and NCO are initialized by sif_sync.

    (e) Toggle config31, bit1 from 2b’0 to 2b’1 to trigger an initialization signal to the fine mixers and NCO.

    (f) Optionally, set config31, bit1 to 2b’0 to be ready to trigger the next initialization signal.

    Regards,

    Neeraj Gill

  • Thank you Neeraj for a very good explanation. 

    In step d) config 31 has bits which allow you to  "auto-sync from SIF register write". 

    What does this exactly mean? Which is SIF register?

    I did not quite understand step f). "set config31, bit1 to 2b’0 to be ready to trigger the next initialization signal." 

    Bit 1 of config 31 is always zero, until I toggle it.

    One more question.

    One of the vendors FPGA board does not have connection to SYNCBP and SYNCBN pins. 

    Will there be any problem? 

    In your data sheet, it says that "it can be left open if not used". 

    Can you please point to the sections of data sheet which has details of these pins?

    Thanks and Regards,

    mallesh