Part Number: ADS42JB69
Hi,
I notice that on the EVAL boards, the SYSREF signals and the SYNC signals are DC coupled with a power supply. Is there reason for the DC coupled? I believe at one point a read that it helps with determining the latency between multiple ADC. I think I also read that if you want a gap controlled or a "one shot sysref" you must provide a DC bias. Can anyone please expand on the subject? Am I somewhat right or totally wrong?
Hi Daniel
Let me address SYNC and SYSREF separately, as there are different concerns in each case.
For SYNC, it must be a DC coupled signal. In normal operation the SYNC signal is a differential 1 nearly all of the time. It only goes to differential 0 when the JESD204B data receiver needs to re-initialize the link and requires the transmitter to re-start the process.
For SYSREF either DC coupled or AC coupled signals are possible, but using an AC-coupled system can require additional system level control of the device receiving the SYSREF, or some static biasing of the SYSREF signal near the receiver. The easiest way to configure a system with one shot or gapped periodic SYSREF is to use a DC coupled interface. This way the transmitter itself provides a consistent logic 0 on SYSREF until the one shot or gapped periodic pulses begin.
One key constraint related to SYSREF is that it must be consistently captured on the same rising edge of CLK to achieve deterministic latency or alignment between multiple converters. For a 250 MHz clock the SYSREF rising edge must be aligned within a 4 ns CLK period (minus allowances for setup and hold time and jitter). To minimize skew variation it is usually recommended that CLK and SYSREF be output by the same IC using similar output formats (both using LVPECL mode for example).
For more background on the SYSREF requirements please review the JESD204B training information here:
I hope this is helpful.
Best regards,
Jim B
