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Linux/DAC38RF80EVM: Realization JESD204B in DAC38RF80EVM

Val Valeriy
Intellectual 430 points

Part Number: DAC38RF80EVM

Tool/software: Linux

Hellow!

Ihave demoboard DAC38RF80EVM.

In the shematic for DAC38RF80EVM on page 5 i see that diff pairs (CLK_LAO_0PSH8 / CLK_LAO_0MSH8), (GTX_CLKPSH8 / GTX_CLKMSH8), (CAR_SYSREFPSH8 / CAR_SYSREFMSH8) are mathed between themselves.

As I understand, according to JESD204B standart, for subclass 1 JESD204B i need only two signals: SYSREF and Device clock (clock for GTX tranceivers) and this signals must be mathed between themselves.

Why in schematic of demoboard DAC38RF80EVM are used 3 signals: one for GTX transceivers, one for sysref and (CLK_LAO_0PSH8 / CLK_LAO_0MSH8).

What is the signal (CLK_LAO_0PSH8 / CLK_LAO_0MSH8) need for?

Best regards, Val.

  • 0
    TI__Guru* 91947 points

    Val,

    The EVM was designed to also be used with Xilinx development platforms. When using this board with a Xilinx board such as the VC707 or KC705, the firmware that was developed uses a separate clock input for REFCLK and Core clock to give maximum flexibility and support all line rates and subclasses with a single programmable design. CLK_LA0 is the second clock source. This is not used by the TSW14J56EVM (Altera based FPGA). The Xilinx IP used in the firmware can be driven by a single clock in many circumstances (see the clocking section of the Xilinx IP product guide for more details).

    Regards,

    Jim

     

  • 0 in reply to jim s
    Intellectual 430 points
    Thank you Jim.
    Regards, Val