LMP90100: configuration and operation

Ahmed Tuna

Part Number: LMP90100

I have read “LMP90100 and LMP9009x Sensor AFE System: Multichannel, Low-Power, 24-Bit Sensor AFE With True Continuous Background Calibration – Datasheet” (SNAS510S – JANUARY 2011 – REVISED JANUARY 2016). It’s a very interesting and useful datasheet for me. I have to design a sensor for weight scale application. In this sensor, the load cell resistive elements are connected in a Wheatstone bridge that has 4 resistors. The value of each resistor is 350 Ohm.

When I was reading this Datasheet, I found in the text a few errors and typos, the list of which I cite below. I kindly ask you to inform me if I am wrong, and to correct the text if I am right. It is very important for me to understand the text correctly, because this is my first work in this field.

In addition, I have questions regarding the description of the chip LMP90xxx, its programming, its configuration and its operation. I will be very grateful if you could provide a feedback. Thank you very much.

The questions.

1. 8.5 Electrical Characteristics. Page 7. VA (Analog Supply Voltage) and VIO (Digital Supply Voltage). It would be better if they are isolated from each other by power supplies (with common ground.) Although it is possible to use the same power source for VA and VIO. Do I understand correctly?
2. 8.5 Electrical Characteristics. Page 7. VREFN (Negative Reference). Can VREFN be less than 0, i.e. negative, for example, -3 V, or its minimum value can be only 0 (GND)? And if VREFNmin=0 (GND), is it possible to use the same power source for VREFP and for VA? Or would it be better if they are isolated from each other by power supplies (with common ground)?
3. 8.5 Electrical Characteristics. Page 8. ANALOG INPUT. VINP Positive Input. VINN Negative Input.

PARAMETER	TEST CONDITIONS	MIN	TYP	MAX	UNIT
VINP Positive Input	Gain = 16 - 128, buffer ON	GND +0.4		VA - 1.5	V
VINN Negative Input	Gain = 16 - 128, buffer ON	GND +0.4		VA - 1.5	V
VIN Differential Input	VIN = VINP - VINN	±VREF / PGA

I use a strain gage with strain gauges connected to the Wheatstone bridge. The output signal from the bridge (VIN - input signal for LMP90XXX) is about 10 mV, ie VINP = 20 mV, and VIN = 10 mV. This is significantly lower than the minimum value specified in the table (GND +0.4). Does it mean that LMP90XXX cannot be used to amplify and convert such input analog voltages? Does it also mean that it is not possible to use internal sources of current IB1 and IB2 for powering the bridge?

4. 8.5 Electrical Characteristics. Page 9. What are the relationships between CLKIN - Internal Clock Frequency (893 kHz) and CLKEXT - External Clock Frequency (3.5717 MHz) with SCLK - Serial Clock (10 MHz)? If, for example, CLKEXT = 2 MHz, SCLK =?

5. 9.3.7.1.1 Types of Background Calibration. 9.3.7.1.2 Using Background Calibration. And 9.3.7.2 System Calibration. Type 1 is used during the operation of the sensor. Type 2 is normally used before starting to set the sensor, in order to set the zero-scale condition. This condition implies that for this specific sensor loading, the zero output code (0x00_0000) shall be set. To set the system reference-scale condition (usually it’s the system full-scale condition in which the sensor loading is 100%, the desired system-calibrated output code shall be 0x80_0000. That is, before starting the operation, it is better to select the Bgalmode mode3, and during the operation of the sensor, it is best to switch to the Bgalmode2 mode. Did I interpret this information correctly?

6. 9.3.7.2.1 System Calibration Offset Coefficient Determination Mode. I can not understand in which case it is necessary to apply the background calibration, and in which case it is necessary to apply the system calibration. There are no recommendations in the datasheet. Or maybe the system calibration is used before the sensor starts operating, and the background calibration during the operation? But then when determining the coefficient of system calibration of the offset, which load should be applied to the sensor?

7. 9.3.7.2.2 System Calibration Gain Coefficient Determination Mode. Step 4 indicates: “Enter the System Calibration Gain Coefficient Determination mode by programming 0x3 in the SCALCN register”. But it doesn’t seem to be correct. In the description of the SCALCN register (Table 22), it is indicated that it is necessary to program into the SCALCN register 0x2, while 0x3 is the reserve. In addition, it is not specified which load should be applied to the sensor when determining the system calibration gain.

8. 9.3.7.2.3. Post-Calibration Scaling. Why is this operation introduced to LMP90XXX? Why do I need to scale after calibration? How does it work? It’s not really clear for me.

9. 9.4.2.1 ScanMode0: Single-Channel Continuous Conversion. Why it is not possible to scan in this mode if the gain is ≥16 and LMP90XXX operates in the background calibration modes BgcalMode1 or BgcalMode2?

10. 9.5.9 DRDYB Case1: Combining SDO/DRDYB with SDO_DRDYB_DRIVER = 0x00. 9.5.10 DRDYB Case2: Combining SDO/DRDYB with SDO_DRDYB_DRIVER = 0x03. And 9.5.11 DRDYB Case3: Routing DRDYB to D6. The Datasheet LMP90XXX does not contain recommendations on the choice of options (Case1, Case2 or Case3) in the development of practical applications. How do these options differ from each other in terms of accuracy, simplicity of hardware and software implementation? What is the main reason why the three options are mentioned (Case1, Case2 or Case3)? Do any of them have specific advantages?

11. 9.5.12 Data Only Read Transaction. It is indicated that «In order to use the data only transaction, the device must be placed in the data first mode. The following table lists transaction formats for placing the device in and out of the data first mode and reading the mode status». What is the data first mode? Which registers’ settings this mode corresponds to? Until now, in the Datasheet LMP90XXX, nothing has been said about this mode. What does the table below mean? Which register? Which bits? The entire section 9.5.12 is not fully clear. There is no description of the operations and transactions that allow this mode to be executed, and there is no description of the mode itself.

12. 9.5.13 Cyclic Redundancy Check (CRC). Why is this operation necessary? What the polynomial CRC value shall be compared to?

13. 9.5.14.2 Reading From Register Example. In the transaction 1, in the upper case, why the write operation is written (0x10), rather than reading (0x90), although reading from the register is done? Is it a mistake?

14. 9.5.15.2 Controlled Streaming Example. A read operation is also performed here, however, both the first and second transactions specify the write operations. Why? Is it a mistake?

15. 9.5.15.2 Reading From Register Example. In the transaction 1 (fig.76), in the upper case, why the write operation is written (0x10), rather than reading (0x90), although reading from the register is done? Is it a mistake?

That’s it for the moment. Perhaps the answers to some of them will help me understand better the features of this LMP90XXX chip, its structure and operation. I apologize for my English. Many thanks in advance for your feedback. Best Regards. Semyon Negovelov. Moscow. 04.15.2018.

The errors and typos.

9.3.7.2.2 System Calibration Gain Coefficient Determination Mode. Step 4 indicates: “Enter the System Calibration Gain Coefficient Determination mode by programming 0x3 in the SCALCN register”. But it's not correct. In the description of the SCALCN register (Table 22), it is indicated that for this purpose it is necessary to program 0x2 into the SCALCN register, while 0x3 is the reserve.
9.5.14.2 Reading From Register Example. In the transaction 1, in the upper case, why the write operation is written (0x10), rather than reading (0x90), although reading from the register is done? Is it a mistake?
9.5.15.2 Controlled Streaming Example. Also in this case, the read operation is performed, however, both the first and second transactions specify the write operations. Why? Is it a mistake?

over 8 years ago

0 Joseph Wu over 8 years ago

TI__Guru** 101185 points

Seymon,

Thanks for your interest in the LMP90100. There's quite a bit to this post, and it's taken me a lot longer than I thought it would to get through this. However, I'll do my best to answer these questions. I'll use the same numbering for the answers as your questions.

1. It is not uncommon to use the same supply for both the analog section (VA) and the digital section (VIO). If you look at the schematic for the LMP90100 Evaluation Board, there are jumper settings to connect VA and VIO to the same source.

2. VREFN generally should not be set below 0V. If you look at the absolute maximum table on page 5 of the datasheet, the reference voltage pins should not be set beyond -0.3V and VA+0.3V. Settings beyond these limits may damage the device, and -3V is well beyond this range.

Yes the positive reference and the analog supply may be the same source voltage. This is common in bridge applications.

3. It depends on how you have the strain gauge connected, but I think you misunderstand the table and the output of the strain gauge. The table means that either input (VINP and VINN) must be within GND+0.4V and VA-1.5V. Assuming VA=5V, this means VINP and VINN must be between 0.4V and 3.5V. Looking at the strain gauge, lets assume this is biased with the full supply from 0 to 5V and the output is +10mV. With many bridges this would mean that the OUTP is about 2.505V while OUTN is 2.495V. Both values are betweent 0.4V and 3.5V so the input of the ADC is in the range for the buffer with higher gain.

It is also possible to power the bridge with the current sources. However, I'm not sure of the specifications of your bridge. You'll just need to make sure each output of the bridge is within the VINP/VINN range of the device.

4. In many of our devices, the SCLK is latched into the master clock domain, so the SCLK needs to be slower than the master clock. However, I'm not familiar with the internal design of this device. While the SCLK may continue to operated at 10MHz, I would scale the SCLK requirement with the master clock frequency and use 5.6MHz as the highest SCLK frequency. At some point there must be some sort of interface between the SCLK and the master clock and scaling it would be safer.

5. There is a document that explains background calibration. You can find it here:

www.ti.com/.../snaa074b.pdf

6. Calibration attempts to adjust for errors in the offset and gain. If you run a calibration, then you try to minimize offset and gain errors at that time. The problem is that offset and gain error may change, especially if the temperature varies.

The background calibration is more useful when the system will be in varying temperature. If you want the system to be more accurate if the temperature changes (say 20°C or so), then you may want background calibration. If you don't expect your conditions to change much through your operation, it's best to run a single calibration and then run with those values (and not continually estimate the calibration values).

You can look at the typical characterisitics curves, you can get a sense of how much the offset and gain error change with temperature. If your operating temperature won't change much, then a single calibration might be your best solution.

7. I believe you are correct. The SCALCN should be set to 0x2 for the System Calibration Gain Coefficient Determination Mode. 0x3 is reserved. When this is set the input should be the reference-scale condition. This is described on page 27 and is generally the system full-scale condition. Basically, this would be the reference voltage. When your input is the reference voltage and you measure it against the reference voltage, this would be the equivalent to the full scale.

8. Post calibration scaling can be used scale the output to a particular value. There may be times this is useful when processing the output data, but it can just as easily be done with a simple multiplication with whatever microprocessor you use.

9. I'm not entirely certain why you shouldn't use BgcalMode1 or BgcalMode2 when operating the gain larger than 16. My guess is that it is likely with such a large gain including the FGA, the offset is less reliable because of noise to get a good estimation of the offset each time.

10. The main difference between these three modes of communication are how you are alerted to new data, and the number of communication lines are used. In Case 1 SDO can be used as an interrupt, but it also requires CSB to enable the data ready indication. In Case 2 SDO can be used as an interrupt, but does not require the CSB to be enabled. With multiple devices, you may need separate SDO lines for each device. For Case 3, you have a separate DRDYB line to indicate data ready. Regardless, these are all fairly similar.

11. Data first mode sets SDO of the LMP90100 so that when SCLK is sent, the data is clocked out as CSB is asserted. Data comes out without having to send and instruction byte.

12. The CRC isn't necessary but you can just use it to verify that the output data was correctly read. There is an MSP430 Interface that has an LMP90100 library that shows the code implementation:

www.ti.com/.../snaa134a.pdf

You can also choose to ignore the CRC byte or not even clock it out.

13-15. I believe that the example is correct and that INST1 should be a write for both writing and reading operations. You can find more information in this post about that:

e2e.ti.com/.../1350144

Later in the post, it references some example code for the MSP430. I listed the application note link previously, but the actual code is zipped here:

www.ti.com/.../snac029

Hopefully, I've answered your questions. I'll still need to find out more about the Data First Mode Transactions. However, there may be more information about this in the zipped MSP430 code. Regardless, this should help get you going.

Joseph Wu

0 Joseph Wu over 8 years ago in reply to Joseph Wu

TI__Guru** 101185 points

Semyon,

Following up on question #11:

Table 6 the command that you would use to set the data first mode. These bits would be the INST2 command for the Data First Mode transactions, allowing for the data to come out first in the readout. After issuing the command, you should be able to read the data directly, up to 8 consecutive registers.

Unfortunately, the apps engineer that got back to me had never used this mode of operation. However, as I mentioned before, there should be more information in the MSP430 example code about how this mode works to read back the data.

Joseph Wu

0 Semen Negovelov over 8 years ago in reply to Joseph Wu

Prodigy 10 points

LMP90100.

Thanks for the answer. But I have new questions.

9.3.7.2 System Calibration.

"The system reference-scale condition is usually the system full-scale condition in which the system's input (or
sensor's loading) would be full-scale and the desired system-calibrated output code would be 0x80_0000
(unsigned 24-bit binary)."

What is the number - 0x80_0000? How does it differ from the number -0x800000? And 0x00_0000 from 0x000000?

10.1.1 Quick Start

"ADC_DOUT is in 24−bit two's complement binary format. The largest positive value is 0x7F_FFFF while the
largest negative value is 0x80_0000. In case of an over range the value is automatically clamped to one of these
two values."

What is the number - 0x7F_FFFF? How does it differ from the number - 0x7FFFFF? And 0x80_0000 from 0x800000?

Thank you.

0 Joseph Wu over 8 years ago in reply to Semen Negovelov

TI__Guru** 101185 points

Hi,

There is no difference between 0x80_0000 and 0x800000 just as there is no difference between 0x7F_FFFF and 0x7FFFFF.

I think that these numbers were accidentally written differently in the datasheet. I think that this change originates from the nomencature used in the Register Map, where most registers were one byte. Several three byte registers were written with a format with 0x00_0000 format and it sometimes carried over into the datasheet text and other times didn't.

Joseph Wu

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LMP90100: configuration and operation