DVALID

Hello 5325088,

Are you referring to the DDC114?

~Leonard  

DDC164 or DDC264。

When you say configure right, is that because you read out the same that you wrote in? Can you tell us what you wrote in?

Also, can you tell us what CLK, CONV and DCLK frequencies are you using?

Does that happen in one device or on several devices?

Thank you!

I read out the same that I wrote in.

spi_send_dat(16'b0010_0110_0000_0000).

CLK=20M;CONV=500;DCLK=10M.

IT happen in  several devices.

Waiting for your reply.

The settings and frequencies look right. Nevertheless, the fact that it happens on several devices points to some issue on the use of the device (it is unlikely that several devices are "broken"). 

Have you followed the power up then RST sequence (section 8.5 of the DS)? I am guessing so as you seem to be able to read back the configuration data. Not sure but probably this wouldn't work if you didn't do thing properly before then.

Is the write order of the bits right? MSB first...

And you finish with the CONV toggling (see figure 30)?

Have you verified with the scope that the frequencies you program are really the ones being applied to the device? Remember that DCLK should be applied only after you get the DVALID. But you seem to say that you don't get even one edge of DVALID, isn't it?

Is the power consumption of the device in line with the spec?

You mean  get DVALID_n is effective then apply dclk,but now  DVALID_n is always 1 How to solve it .

I meant to say that you seem to be clocking DCLK all the time, but you should start clocking it in response to a /DVALID going to zero, and stop giving DCLKs as soon as you are done reading the data. Basically, with the edge of conversion, the internall ADC starts converting (speed set by CLK). When done, it gives a /DVALID (pulse from one to zero). When you clock DCLK, the device will shift one bit out and reset /DVALID to high, its default state (till another ADC conversion is done). Then you keep giving DCLKs to shift out the rest of the data. Once you got it all, you stop DCLK. And everything waits till the next DVALID, when you start again. I have a feeling that if you keep giving DCLKs, there may be some timing violation that creates the issue that you see, but I am just guessing... Please check if it works for you...