ADS52J90EVM: ADS52j90 FPGA CLK

Hello Praveen 

Thanks alot for your response. 

I dont have TSW14J56EVM capture card. i am using ZCU102 xilinx board to read samples.

My plan is to check first if the ADC signals are coming as per the JESD configuration. and then i will connect these signals with the JESD ip core in Vivado. 

The Vivado IP core accepts two clocks

1- Ref Clk

2- Glb Clk

ADS52j90 EVM also gives two clock 

1- FPGA_GTXCLK P/M 

2. FPGA CLK  P/M

I am connecting FPGA_GTXCLK  to the Ref CLk  and FPGA Clk to GLB clk. 

Thats why it was important for me to see if the both clocks are functional .

Do you think i am going in the right direction ? 

Best Regards

Rizwan 

Hi Praveen 

Thanks alot parveen for your reply. I have attached the photo of my EVM. 

Currently i am supplying 120 Mghz at J75

I have checked some Vivado reference designs, and in those designs clock signals are connected as i described above. That's Why i wanted to know why i am not able to see the clock ( FPGA_CLK) on evm. this clock is also observableon test point TP22 and TP21. 

Thanks for assistance :)

Attached Photo 

Hi Parveen 

So i dig a little deeper in to it. 

FPGA CLK  ( on ADC EVM ) is coming from DCLKOUT8p ( from LMK04826 ). so LMK04826  is generating all the clocks for the ADCs. i.e. GTX clk, sysref etc.  

I checked the datasheet of LMK04826 to confirm if i am setting the register for the DCLKOUT8p  correctly. the register address is 120x and its value is 0x04 ( clock divided by 4 ) . it means that the register setting is also correct. 

Could you please comment on it, where could be the problem with this clock. ? 

Best Regards

Rizwan