Other Parts Discussed in Thread: ADS52J90
Hello
I am using TI's High speed ADC board ADS52J90EVM. I am using ZCU102 to read ADC samples. I am not able to get ADC samples at the output of jesd ip core in vivado.
I have invested a lot of time in it, it seems that i am not able to configure the ADC properly.
Attached is my ADC configuration file, ADS52J90_16ch_SINE_4L_12x_12b_GBLCLKDIV1_FSDIV3_SYSREFDIV24_20x.cfg
according to my understanding this congfiguration file has the following parameters
1- Num_ADC_PER_LANE = L= 4
2- F = 6
3- K = 3
4- SER_DATA_RATE = 12x
5- N’ = number of bits = SER_DATA_RATE= 12
6- ADC_RES = 12 bit
7- SINGLE CONVERTER PER OCTET MODE = 0
8- Scramebled disabled ( ADC address 52 h = 0 )
My Question is
1- What would be the Line Rate = ??
2- How much frequency I should apply externally = External Clock = ?
I need this information so that i can configure the following parameters in Vivado core. Could you please help me out in setting the right parameters.
2620.ADS52J90_16ch_SINE_4L_12x_12b_GBLCLKDIV1_FSDIV3_SYSREFDIV24_20x.cfg