Hello,
I plan on using the ADC12D1600 for a custom board design. I would like to use this device as a dual channel ADC with 1.6 GHz sampling speed per channel. One problem is that the FPGA to which this device interfaces with has limited LVDS data pins. So i was planning to do the following:
1. Use this device in Non-Demux Non-DES mode (Figure 2 of datasheet). Looks like in this mode, i can use just the DI and DQ data bus and get the ADC data with up to 1.6 GHz sampling speed per channel. I can ignore the DId and DQd data bus. Data can be sampled in the FPGA, per channel, using DCLK clock (half-rate of sampling clock) with DDR registers. Is my understanding correct ?
2. If the above is correct, can i leave the DId and DQd data bus pins floating for the ADC ? Or do i need any special termination for them ? I cannot tie these pins to the FPGA.
Your response is highly appreciated.
Thanks,
Arvind
