DAC37J84: Phase noise under low temperature

Hello Takumi-san,

I would check to see if the phase noise of the LMK04828 clock is also being impact at cold temperature.Please ask the customer to measure the LMK04828 clock to the DACCLK input of the DAC38J84. I would like to make sure the clock source is clean before further move into DAC38J84 debug.

Typically, the DAC phase noise performance is limited by the clock source and/or the clock drive (internal to the DAC) power supply quality

at this point, if we are safe to rule out the LMK04828 quality, then we can check:

1. if the on-chip PLL is used, please check if the PLL is still within the optimal lock range. You can read back the PLL loop filter voltage through register config 0x0031. We may need to adjust the PLL voltage (i.e. VDDPLL18) to slightly higher of the specification and check if it fixes the problem. (see below for ATEST method). 

2. Use the ATEST pin on the device, program register 0x001B to walk through some of the critical ATEST nodes. Typically, the VDDCLK voltage are sensitive to LDO/DC/DC power supply noise. Perhaps at cold temperature there are increase in noise and also drop in the voltage level. 

If the LDO powering the VDDCLK has noise at cold temperature, then the noise will modulate onto the power supply of the clock buffers internal, and hence modulating onto the output.

To ensure the voltage level at the device internal nodes are correct, please program 0x0027 to check all the nodes to make sure they are within the specification.

-Kang

Tamkumi-san,

regarding your question:

Takumi Suzuki1 said:

I do not understand well what you point ".......please program 0x0027 to check all the nodes...".

What is "0x0027" register? I suppose this is the register reserved..

I was referring to the ATEST programming. Basically, the engineer may use a voltmeter with respective to the ground to measure the ATEST pin (K9 pin of the device) and measure the internal nodes. The internal nodes are programmed by the ATEST registers in the 0x001b (config27) register. I apologize I made a typo on the ATEST register. 

I have pasted the register information below:

Takumi-san,

The reason that I asked the customer to raise the voltage slightly is because there may be PCB resistance and power supply filter resistance at the power supply node (LDO or DC/DC). With the current drawn, the resistance created voltage drop and may not provide the right level at the operation. I ask the customer to raise the voltage slightly such that when the chip is turned on, the voltage level falls within the specification. The customer needs to be careful since before the chip is turned on (without current drawn), the voltage may be higher since there are no voltage drop. Therefore, the power supply may still need to be within the higher range of the specification, even with the chip turned off.

The ATEST procedure will help identify if there are significant voltage drop at the problematic temperatures. Perhaps the LDO need to be adjusted at such temperature.

-Kang