The ADS1271B is used on a new design with 16 devices operating synchronously. The device is controlled in the Frame-Sync mode, and can be operated in either the High-Speed or High-Resolution mode. To simplify the issue here, only the High-Speed mode is addressed. although the same symptom occurs in either mode.. An Altera Cyclone-II FPGA provides the digital interface. This device must be configured at power-on, and requires from 10-100 milliseconds to complete this operation. During configuration, all outputs are tristated. The problem is this: During several days of working with the prototype, the DOUT pin has been consistently Low; as though the device were stuck in Power-Down mode. To date, a High level bit has not been seen on this pin. Connections and timing are shown on Sh.2. - 2 - ADS1271B; Operating in High-Speed mode with Frame-Sync control. Pin Signal Type State Comments 1 IN+ Inp Various; 2 IN- Inp See note
1
3 AGND Gnd AGND
4 AVDD Pwr +5.00V
5 MODE Inp Low High-Speed Mode
6 FORMAT Inp High Frame-Sync control
7 SYNC/PDWN Inp High Pulsed Low to synchronize
2
8 DIN Inp DGND
9 DOUT Out ---
No nonzero data; Always Low.
10 FSYNC Inp Pulse
11 SCLK Inp 8 CLKs See timing diagram and note
3
12 CLK Inp 256/Sample
13 DVDD Pwr +1.80V
14 DGND Gnd DGND
15 VREFN Inp AGND
16 VREFP Inp +2.500V
1
Two typical conditions:
1. IN+ = IN- = +2.500V (Midscale) 2. IN+ = +3.662; IN- = +1.337 (Vin = +2.325; 93% PFS; Vcm = +2.500V).
2
SYNC/PDWN held low until CLK, SCLK and FSYNC are established. Forcing High or Low has no effect.
3
CLK, SCLK and FSYNC are applied continuously after FPGA configuration is completed.
