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ADC32J44: Setting the “K” Value

Richard Elmquist

Mastermind 45250 points

Part Number: ADC32J44

My customer has asked the following:

We noticed in the datasheet that K is configurable through SPI. We would like to know what the range of this configuration parameter is. Can we set it to 0 and have only 1 frame per LMFC.

I am not sure on this, but the note in Register 31h seems to indicate that the lowest value is 8. Can you go into more detail concerning the K values and how they relate to the LMFS parameters of JESD204B.

Thanks for your help with this!

Richard Elmquist

over 6 years ago

0 jim s over 6 years ago

TI__Guru* 91947 points

Richard,

Per the JESD204B standard:

LMFC period must be longer than the longest link delay. K parameter (frames/multiframe) determines LMFC period.

1 < K < 32

17 < K*F < 1024

Regards,

Jim

0 Richard Elmquist over 6 years ago in reply to jim s

TI__Mastermind 45250 points

Jim,

Thanks for your response. I will send it to the customer.

He also asked the following question:

If we use the ADC in subclass 0, does SYNC~ have to be synched to the system clock and respect the setup/hold time of the ADC input?

It is mentioned that in subclass 0 this signal is not timing critical so just wanted to confirm.

http://www.ti.com/lit/ml/slap161/slap161.pdf

Thanks for your help with this!

Richard Elmquist

0 Richard Elmquist over 6 years ago in reply to Richard Elmquist

TI__Mastermind 45250 points

Jim,
Have you been able to look at the further questions from the customer?
Thanks for your help with this!
Richard Elmquist

0 jim s over 6 years ago in reply to Richard Elmquist

TI__Guru* 91947 points

Richard,

I have past this on to the design team but have not heard back from them yet.

Regards,

Jim

0 Richard Elmquist over 6 years ago in reply to jim s

TI__Mastermind 45250 points

Jim,
Are there any updates from the design team?
Thanks for your help with this!
Richard Elmquist

0 jim s over 6 years ago in reply to Richard Elmquist

TI__Guru* 91947 points

Richard,

SYNC~ does not have to be synched to the system clock and respect the setup/hold time of the ADC input.

Regards,

Jim

0 Richard Elmquist over 6 years ago in reply to jim s

TI__Mastermind 45250 points

Jim,
Thanks for your help with this!
Have a wonderful day!
Richard Elmquist