ADC32J44: SYNC~ signal timing for subclass0

Ben__

Part Number: ADC32J44

Do we need to meet setup/hold time of the SYNC~ signal when working in subclass 0? Reason is we have HW components that might make this not possible.

If that is required, can we drop the SYNC~ signal and use soft synch instead? (using Register 3A - SYNC REG, SYNC REQ EN)

Thank you

over 8 years ago

0 Jim Brinkhurst1 over 8 years ago

TI__Mastermind 44680 points

Hi Ben
We have received your question. Someone will provide a more detailed response soon.
Best regards,
Jim B

0 jim s over 8 years ago in reply to Jim Brinkhurst1

TI__Guru* 91947 points

Ben,

If you are only using one ADC, this should not be a problem to use the software controlled SYNC. You will have to make sure the FPGA is receiving valid K characters on all lanes before setting SYNC back high though when brining up the link.

Regards,

Jim

0 Ben__ over 8 years ago in reply to jim s

Prodigy 50 points

Great thanks, do you recommend connecting this pin to static HIGH then?

0 jim s over 8 years ago in reply to Ben__

TI__Guru* 91947 points

Yes. As a backup plan, you may want to have a test point on this pin just in case you decide to control it with your FPGA.

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ADC32J44: SYNC~ signal timing for subclass0